A Study of Oxide Defects in III-V MOS Devices using Electrical and Mathematical Methods

III-V compound semiconductors are considered as potential channel materials for replacing Silicon in commercial logic devices. One of the major roadblock is the difficulty in developing the gate stack of sufficiently high quality to enable a III-V metal-oxide-semiconductor (MOS) device with high and reliable On performance. The defects in high-k dielectrics are, therefore, one of the key areas of focus for research on III-V based MOS devices. Due to the pervasive nature of the impact of these defects on the device performance, it becomes extremely important to gain a better understanding of these defects in order to explain various physical phenomena observed through characterization techniques in use today.

This work, therefore, concentrates on the investigation of these defects through electrical and mathematical methods. A detailed investigation on 2 experimental observations, in particular, form the major part of this thesis: the frequency dispersion in the accumulation region, and hysteresis in the capacitance of a III-V MOS capacitors (MOSCAPs). The frequency dispersion is ascribed to a 2-step inelastic border trap (BT) capture/emission process based on the experimentally observed temperature dependence and a new, physically correct, model is proposed and validated for BT-electron interaction. Furthermore, from the mathematical model, a new quality metric (for bench-marking), and a new set of equations for defect density extraction is developed. Their applicability and efficiency is validated for different gate stacks.

The hysteresis, irrespective of the gate stack, is found to be dependent on the measurement parameters and is ascribed to a broad defect distribution in the III-V gate stack, a property shown to be very specific to these materials. A mathematical model is developed to confirm the hypothesis which shows a very close correlation with the experimental data. Interestingly, this effect is found to be useful in extracting the information on the defect density in the gate stack. A characterization methodology is developed to use this feature and is validated on different dielectric stacks. It is observed that Al2O3 has a very broad defect distribution across the InGaAs band-gap which explains the poor reliability shown by MOS devices with this dielectric.

The model is also used to understand and predict the impact of various engineering techniques on reliability improvement. It is predicted that an improvement in the energy profile of the defect distribution (and not the density) would produce a significant boost in reliability. This hypothesis is experimentally shown to be confirmed by a case study of a gate stack consisting of a new interfacial layer. It is demonstrated, using the hysteresis model, that due to a combined effect of a favorable energy misalignment and better defect profile, for the first time, a reliability performance very close to the target could be achieved on III-V MOS devices.