Cross-Layer Optimization for Power-Efficient and Robust Digital Circuits and Systems

In modern deep scaled CMOS ICs, the process, voltage and temperature (PVT) variations result to a randomized variation of the transistor’s parameters. The variability is becoming so large that, by adapting conventional corner based design methodology, the design margin introduced by variation might over-kill the benefit of scaling. This PhD project aims to exploit the design margin that circuit might experience none or small amount of error, yet delivers qualified output.