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Project

Modelling, exploration and technology assessment of steep-subthreshold-slope transistors for N5/N3 CMOS power-performance scaling

For more than half a century, semiconductor integrated circuits (ICs) have evolved with the miniaturization of transistor footprint, the improvement of chip performance and the reduction in operating power, which are collectively referred to as “power-performance-area” (PPA) scaling. Moving on to the sub-deca-nm scaling regime, the main workhorse of the IC industry, Si MOSFET, increasingly struggles to keep up with the unrelenting demand for higher computing performance and/or lower power- (or energy-)consumption. A fundamental limitation of MOSFETs, the above-60 mV/dec subthreshold swing (SS) has impeded the desired supply voltage- (VDD-) and power-reduction while delivering diminishing drive current gain from channel length scaling. The SS limit of MOSFET, also known as “Boltzmann’s tyranny”, puts the continuation of logic PPA scaling at stake.
Lately, steep-slope transistors have been proposed as a game changer to overcome the scaling predicament of MOSFETs. With a sub-60 mV/dec SS, they are envisioned capable of reducing the VDD and power consumption without losing performance, or alternatively of delivering higher performance at no extra cost of power.
This thesis focuses on two representative steep slope transistors: the tunnel FET (TFET) and the steep-slope ferroelectric FET (SSFeFET). We concern ourselves with the SPICE-level compact modelling, device physics interpretation and logic-circuit PPA exploration of these two proposed devices.
The TFET breaks the SS limit by resorting to band-to-band tunnelling (BTBT). The “Zener tunnelling diode” nature of TFET brings high hope for a sharp SS and a low OFF-current, but also casts doubt on the available ON-current. Over the past decade, numerous device-level optimizations have been proposed for TFET and (partly) demonstrated on hardware, that involve extensive material-/architectural-innovations. This thesis devotes its first part to a holistic, nonideality-aware circuit performance-energy evaluation of present and projected TFET technologies and benchmarks them versus conventional Si MOSFETs.

The second part of the thesis revolves around the SSFeFET, a device that amplifies the channel charge response to the applied gate voltage through introducing a dynamic threshold voltage (VTH) shift using a ferroelectric gate oxide. The SSFeFET shares with non-volatile memory- (NVM-)FeFETs a similar metal-ferroelectric-insulator-semiconductor (MFIS) configuration and also a polycrystalline (doped-/alloyed-) HfO2-based ferroelectric gate oxide. Yet both the physical understanding and the experimental interpretation of the SSFeFET remain highly debated. This thesis therefore proposes to develop a physical interpretation of the hysteretic, steep-slope operation of the SSFeFET based on the NVM-FeFET and to further corroborate it. Moreover, we aim to shed light on the relevance of a hysteretic steep slope transistor in general to logic PPA scaling.

Date:31 Mar 2017 →  6 Jul 2022
Keywords:CMOS scaling, Tunnel FET, device-circuit co-design, Technology Computer Aided Design (TCAD), Compact modelling, ferroelectricity
Disciplines:Nanotechnology, Design theories and methods
Project type:PhD project