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Researcher
Geert Hellings
- Disciplines:Nanotechnology, Design theories and methods
Affiliations
- Assiocated Division ESAT-INSYS (INSYS), Integrated Systems (Division)
Member
From1 Aug 2020 → 31 Dec 2011 - Electronic Circuits and Systems (ECS) (Division)
Member
From1 Aug 2020 → 30 Nov 2011 - Associated Section of ESAT - INSYS, Integrated Systems (Division)
Member
From19 Nov 2007 → 31 Dec 2011 - Department of Electrical Engineering (ESAT) (Department)
Member
From16 Apr 2005 → 18 Nov 2007
Publications
1 - 10 of 74
- Strained c:Si0.55Ge0.45 with embedded e:Si0.75Ge0.25 S/D IFQW SiGe-pFET for DRAM periphery applications(2016)
Authors: Geert Hellings
Pages: 255 - 258 - Impact of local interconnects on ESD design(2015)
Authors: Shih-Hung Chen, Geert Hellings, Roman Boschke
Number of pages: 4 - On and off state Hot Carrier reliability in Junctionless high-K MG gate-all-around nanowires(2015)
Authors: Geert Hellings, Hiroaki Arimura, Jacopo Franco
Pages: 366 - 369 - ESD protection diodes in optical interposer technology(2015)
Authors: Roman Boschke, Guido Groeseneken, Shih-Hung Chen, Geert Hellings
Pages: 1 - 4 - Characterization of self-heating in high-mobility Ge FinFET pMOS devices(2015)
Authors: Geert Hellings, Guido Groeseneken
Pages: 60 - 61 - ESD characterization of gate-all-around (GAA) Si nanowire devices(2015)
Authors: Shih-Hung Chen, Geert Hellings, Roman Boschke, Guido Groeseneken
Pages: 362 - 365 - VFTLP characteristics of ESD protection diodes in advanced bulk FinFET technology(2015)
Authors: Shih-Hung Chen, Geert Hellings, Roman Boschke, Guido Groeseneken
Pages: 9 - 1 - Gate-All-Around NWFETs vs. Triple-Gate FinFETs: Junctionless vs. Extensionless and Conventional Junction Devices with Controlled EWF Modulation for Multi-VT CMOS(2015)
Authors: Geert Hellings
Number of pages: 2 - ESD characterization of planar InGaAs devices(2015)
Authors: Roman Boschke, Geert Hellings, Shih-Hung Chen, Ali Reza Alian, Jacopo Franco, Guido Groeseneken
Pages: 3 - Local CDM ESD protection circuits for cross-power domains in 3D IC applications(2014)
Authors: Shih-Hung Chen, Geert Hellings, Roman Boschke, Guido Groeseneken
Pages: 781 - 783
Patents
1 - 5 of 5
- Method for fabricating finfet technology with locally higher fin-to-fin pitch (Inventor)
- Breakdown-based physical unclonable function (Inventor)
- Breakdown-based physical unclonable function (Inventor)
- Scalable quantum well device and method for manufacturing the same (Inventor)
- IMPLANT FREE QUANTUM WELL TRANSISTOR, METHOD FOR MAKING SUCH AN IMPLANT FREE QUANTUM WELL TRANSISTOR AND USE OF SUCH AN IMPLANT FREE QUANTUM WELL TRANSISTOR (Inventor)