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Electrical Modelling and Characterization of Extended Defects in n Type InxGa1-xAs System

The growth-induced extended defects such as misfit dislocations, threading dislocations and stacking faults in the n-type InGaAs system (indium content 30% ∼ 80 %) have been comprehensively and systematically studied with respect to their electrical properties and device impact (pn junctions). In this thesis, the n-type InGaAs layers are carefully grown on SI-InP or SI-GaAs substrates by the MOCVD technique to obtain a varying defect density and defect types, followed by pn diode fabrication for the purpose of electrical characterization. The defect structural information is revealed by SEM(ECCI), TEM, AFM and XRD.

Two different sets of samples are selected for further study. The first set is based on a fixed indium content in the active n-type In.53Ga.47As (Nd ∼ 1−2×1016 cm−3) with different δTD(=TDD) and MD+SF line density varying from 105 to 2 × 109 cm−2. These defects are intentionally introduced by growing an In.xGa.1−xAs (x=0.13 ∼ 0.53) n+ layer on top of the substrate and can propagate/slip into the p+/i- In.53Ga.47As layers, grown on top of the n+ layer. By XRD analysis, it is verified that the n- layer of interest is a non-strained layer. The JA−Vr curves of the corresponding pn junctions show a gradual increase of the reverse current when the EDDs become high. After careful comparison, the reverse current (∝ τ−1 g ) and recombination current (∝ τ−1 r ) is roughly proportional to the δ−1 TD with a corresponding minority capture-cross section of 5 × 10−16 ∼ 5 × 10−17 cm2 and a mid-gap level of the associated G-R centers. These TD-induced G-R centers have very strong electrical field (Fmax) enhancement when Fmax exceeds 6 ∼ 8 × 104 Vcm−1, which can be modeled by the TAT mechanism with a 10 times smaller tunneling effective mass (mt). The mt feature has been explained by the additional internal
transitions with rate Γi prior to the TAT process. The Fmax-enhancement and the TD-related G-R centers have been further confirmed by the DLTS and PL measurement, showing consistent results regarding the trap levels, σp and NT /δTD.

The second set of InGaAs samples is designed with the full In.xGa.1−xAs p+/i/n+ stacks on top of the SI-InP substrate with fixed x=0.47 ∼ 0.73. The dominant defects are mainly based on the magnitude of latticemismatch and the type of relaxation (tensile/compressive), yielding α-MD+SFs (tensile, small lattice-mismatch), β-MD+screw dislocations (compressive, small lattice-mismatch) and TD+MD (two types, large lattice-mismatch). The generation/recombination current from the related pn junctions are also dominated by the defect-induced current. The same electrical enhancement factor (ΓTAT ) is observed for all samples at reverse current, suggesting the presence of the same TAT mechanism and TD-dominated G-R current for the
second set of samples. Besides, we have noticed that the samples with rich SFs+partial dislocations have generally a smaller τg and τr compared with the predicted lifetime trend by only considering TDs, indicating that SFs+partial dislocations should be electrically active and contribute to the current leakage. However, we could not identify the underlying trap level in DLTS analysis.

DLTS has been performed on all samples to analyze/identify the ED-related traps. The H1 and E2 traps are confirmed to belong to a single broad density of occupied states straddling the center of band-gap and are assigned to the TD-related traps as mentioned above. Except the H1/E2 traps, three additional ED-related trap levels E1, H2 and H3 are also observed, which are respectively assigned to the α-MD, screw dislocations and β-MD. By combining with the related literature, we have derived the evolution of these traps in function of the indium content, as shown in equation 5.5, 5.6 and 5.8. Overview figures of ED-related traps in the InGaAs system are also shown in figure 5.19 (electron traps) and 5.20 (hole traps). In addition, detailed capture kinetics and the distribution of the multi-states of ED-related traps are also examined, indicating the band-like feature of E2/H1 and H2 levels and the localized states for E1 and H3. The strong Fmax enhancement is also validated by the double-correlated DLTS, showing a strong connection with the JV − Vr(T) characteristics.

Based on the extracted trap parameters above, the transport behavior of ED-related traps has been examined using the commercial Sentarus-TCAD software in combination with the advanced model reported by Scheinemann and Schenk. We have developed a new dynamic method for the calculation of the occupation probability (ft) which can self-consistently solve the ft problem as well as derive the potential barrier under the framework of MSC. The convertibility between our system and the literature approach has also been demonstrated. Although the fitting results of point defects (reference sample) exhibit good agreement with the experimental behavior, the modeling results of ED-related traps are contradictory to the experimental data. After several trials and error, we have concluded that a more complex model including the Fmax enhancement and the multi-states internal transition are crucial to have a successful modeling. Therefore, we have stepped back to use an
alternative simple method (SRH) which only considers the effective trap level and G-R lifetime in the whole system without the knowledge of the internal transitions within the ED band of states. In that case, decent fitting results to the experimental JV − Vr(T) ones can be achieved.

Date:23 Aug 2017 →  11 Jan 2022
Keywords:III-V, DLTS, TCAD, InGaAs, Materials characterization, electrical state, Defect
Disciplines:Ceramic and glass materials, Materials science and engineering, Semiconductor materials, Other materials engineering
Project type:PhD project