Vertical III-V Gate-all-around Nanowire MOSFETs: Process Integration and Contact Resistance Study

The key to continuous improvement in MOSFET performance is scaling. However, device down-scaling poses some fundamental limitations. One of the common challenges of transistor scaling is the short-channel effect, where a gate-all-around architecture (GAA) could help. In addition, it is getting difficult with lateral devices to extend the technology roadmap beyond sub-10nm technology nodes while respecting the rules of scaling. A vertical architecture, hence, is essential to effectively de-couple gate length scaling and active-area scaling. Vertical nanowire MOSFETs with GAA are the ultimate solution.

Another challenge of down-scaling is the increase in power dissipation with transistor density. This calls for a trade-off between operating voltage and switching speed. New channel materials are, thus, necessary to afford voltage reduction without compromising the performance. III-V compound semiconductors are attractive candidates that allow high mobility charge carriers at low operating voltages. Therefore, vertical GAA III-V nanowire devices will be the focus of this study.

The PhD work is aimed at achieving the following

- Process integration of vertical III-V nanowire devices with top-down approach

- Study the effect of EOT scaling, nanowire dimension scaling and channel surface pre-treatments on device performance

- Address the contact resistance problem in these nanoscale devices by developing a suitable nanowire resistor test vehicle

- Electrical characterization and parameter extraction of the nanowire resistors