Unified Physics-Based Model of Degradation of FinFETs and Nanowire FETs for beyond 7 nm Technologies

Following Moore’s law, the semiconductor industry introduces a new MOSFET technology approximately every two years. While originally simple geometrical scaling was sufficient to obtain doubling of the number of transistors on a chip with increased performance every new generation, innovations like mechanical strain, high-k metal gates, and finFETs were needed in the last one to two decades to continue the performance improvement. For the technologies beyond the 5 nm node, gate-all-around transistors, like nanowire (NW) and nanosheet (NS) FETs, are considered. Recently, a forksheet (FS) FET architecture was also proposed. FS FETs consist of nFETs vertically stacked on one side of a dielectric wall and pFETs vertically stacked on the other side of the same wall. The FS FET architecture allows to decrease the separation between pFETs and nFETs (p-to-n separation) and thus to further scale logic cells. The reason is that the presence of the wall makes the architecture more tolerant against certain processing inaccuracies which currently determine the minimum p-to-n separation.

During operation, transistors inevitably age and degrade. These processes are linked to the charging of existing defects and creation of new traps in the gate dielectric and at the channel/dielectric interface. At high drain bias, highly energetic (= hot) carriers can break interfacial Si-H bonds, a reliability problem called Hot-Carrier Degradation (HCD). In the latest technologies, HCD was reported to be a reliability problem of growing concern. In this thesis, we first review HCD history and physics. The main objective of the thesis is then to investigate HCD in NW, NS and FS FETs (beyond 5 nm devices) using simulations. As a secondary objective, we study the defects induced by hot-carriers (HCs) using high temperature HC anneal measurements. The anneal study is of relevance for the models used in the HC simulations and is performed on planar devices in a commercial 40 nm technology.

In the HC anneal measurements, we confirm the recovery of HCD on chip and that it can be described using the model of Stesmans for passivation of Pb-centers in molecular H2, in line with previous reports in the literature. We then observe the anneal to be gate bias dependent. We also perform multiple HC stress and anneal measurements repeated on the same device and we develop an extension of the Stesmans model to describe this cycled HC anneal. We find that there is no correlation between Si-H bond dissociation and passivation energies and that the distribution of bond passivation energies deviates from the Gaussian shape from the second anneal cycle onwards.

As the first part of the HC simulations, we study which physical mechanisms are responsible for HCD in each part of the (Vg, Vd) stress bias space. To this end, we compare HC simulations to measured HCD data from a fabricated NW FET. We find that for the stress condition Vg > Vd, HCD can be modeled without considering impact ionization (I/I) in the simulations. The degradation in this region is due to the multiple particle (MP) mechanism of Si-H bond breakage. For Vg < Vd, discrepancies between the simulated and measured HCD are observed when excluding I/I in the simulations. Although the simulation result improves when considering the possibility that holes generated by I/I create defects, an exact quantitative match between simulations and measurements is not obtained for the Vg < Vd stress regime.

As the second part of the HC simulations, we compare NS FETs to FS FETs at the worst case HC condition. For both device geometries, we find that I-V degradation induced by interface state generation decreases with increasing sheet width. Since FS FETs can be made wider than NS FETs due to their reduced p-to-n separation, FS FETs show lower HCD when considering roadmap dimensions.

As the last part of the HC simulations, we study the trapping of HCs in the FS FET wall. Since the intended material for the wall (i.e. SiN) is used as charge trapping layer in non-volatile memories, trapping in the wall is a potential reliability concern. Using the best possible estimate of the SiN charge trapping parameters and considering device dimensions from the roadmap, we find that I-V degradation due to trapping in the FS FET wall is significantly smaller than due to trapping in the gate stack. Consequently, we do not foresee FS FET wall trapping to be a reliability concern for the further development of the FS FET architecture.