A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC

This paper presents a 6-bit very high-speed, low-power digital-to-analog converter (DAC). It is based on a current steering binary weighted architecture and achieves 10-bit static linearity without calibration. Due to the use of a pseudo-segmented structure instead of a thermometer decoder, the operating speed of the converter can be up to 4.5 GS/s. The DAC occupies 0.4 mm × 0.5 mm in a standard 130 nm CMOS technology. A spurious-free dynamic range (SFDR) of more than 36 dB has been measured over the complete Nyquist interval at sampling frequencies up to 3 GS/s. The power consumption at a 3 GHz clock frequency for a near-Nyquist sinusoidal output signal equals 29 mW. © 2008 IEEE.

Publication year:2008

BOF-keylabel:yes

IOF-keylabel:yes

BOF-publication weight:6

CSS-citation score:2

Authors from:Higher Education