Electrical modeling and characterization of through silicon via for three-dimensional ICs

Three-dimensional ICs provide a promising option to build high-performance compact SoCs by stacking one or more chips vertically. Through silicon vias (TSVs) form an integral component of the 3-D IC technology by enabling vertical interconnections in 3-D ICs. TSV resistance, inductance, and capacitance need to be modeled to determine their impact on the performance of a 3-D circuit. In this paper, theRLC parameters of the TSV are modeled as a function of physical parameters andmaterial characteristics. Models are validated with the numerical simulators like Raphael and Sdevice and with experimental measurements. The TSV RLC model is applied to predict the resistance, inductance, and capacitances of small-geometry TSV architectures. Finally, this paper also proposes a simplified lumped TSV model that can be used to simulate 3-D circuits. © 2009 IEEE.

Publication year:2010

BOF-keylabel:yes

IOF-keylabel:yes

BOF-publication weight:1

CSS-citation score:4

Authors from:Government, Higher Education