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Publication

A Multi-Bit Neuromorphic Weight Cell Using Ferroelectric FETs, suitable for SoC Integration

Journal Contribution - Journal Article

© 2013 IEEE. A multi-bit digital weight cell for high-performance, inference-only non-GPU-like neuromorphic accelerators is presented. The cell is designed with simplicity of peripheral circuitry in mind. Non-volatile storage of weights which eliminates the need for DRAM access is based on FeFETs and is purely digital. The multiply-and-accumulate operation is performed using passive resistors, gated by FeFETs. The resulting weight cell offers a high degree of linearity and a large ON/OFF ratio. The key performance tradeoffs are investigated, and the device requirements are elucidated.
Journal: IEEE Journal of the Electron Devices Society
Volume: 6
Pages: 438 - 448
Publication year:2018