Test structures for characterization of through-silicon vias

3-D chip stacking using through-silicon vias (TSVs) requires accurate characterization of the TSV, the thinned silicon, and the stacked dies. This paper proposes a set of test structures specifically designed to address the electrical characterization of TSV in terms of resistance, capacitance, leakage, yield, and their impact on the 2-D interconnects of the stacked dies. Examples of the use of these structures are presented, and the observed electrical behaviors are explained with the support of FIB cross-section images. © 1988-2012 IEEE.

Publication year:2012

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CSS-citation score:1

Authors:International

Authors from:Government, Higher Education