< Back to previous pagePublication Capacitance reduction technique for through silicon via (TSV) in p-Si substrate Journal Contribution - Journal ArticleJournal: IEEE Electron Device LettersISSN: 0741-3106Issue: 6Volume: 31Pages: 549 - 551Institutional Repository URL: https://lirias.kuleuven.be/1732621Authors/publisherGuruprasad Katti (First author)Michele Stucchi (Author)Christina De Meyer (Author)Wim Dehaene (Last author)Research unitsAssociated Section of ESAT - INSYS, Integrated Systems(Division)KU LeuvenAssiocated Division ESAT-INSYS (INSYS), Integrated Systems(Division)KU LeuvenElectronic Circuits and Systems (ECS)(Division)KU Leuven
