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A 11 mW 68dB SFDR 100 MHz bandwidth delta-sigma-DAC based on a 5-bit 1GS/s core in 130 nm

Book Contribution - Book Chapter Conference Contribution

This paper presents a delta-sigma current-steering digital-to-analog converter implemented in a standard 130nm CMOS technology. The 5-bit core DAC provides 13-bit static linearity without calibration, using only 0.44mm 2. The delta-sigma converter achieves 68dB SFDR over a 100MHz signal bandwidth at 1GHz sampling frequency. A novel very low power thermometer decoder was used, resulting in a power consumption of llmW. In terms of power efficiency this converter outperforms all comparable D/A converters published in open literature. The design demonstrates the viability of multi-bit delta-sigma D/A converters as an alternative for Nyquist-rate DACs in highly integrated broadband applications. It also shows that in deep sub-micron processes the use of a delta-sigma converter extends the usable bandwidth for D/A converters. © 2008 IEEE.
Book: European solid-state circuits conference
Pages: 214 - 217
ISBN:978-1-4244-2361-3
Publication year:2008