Local CDM ESD protection circuits for cross-power domains in 3D IC applications

CDM ESD events can be a potential threat to SoC designs or heterogeneous 3D ICs with multiple power domains. Inter-layer (or interface) circuits may need a local CDM ESD clamp that can prevent the unexpected failure under CDM ESD stress. In this letter, two local CDM ESD clamp circuits are proposed. They show better clamping efficiency under 2-ns vfTLP stress. © 2001-2011 IEEE.

Publication year:2014

BOF-keylabel:yes

IOF-keylabel:yes

BOF-publication weight:1

CSS-citation score:1

Authors:International

Authors from:Government, Higher Education