ESD characterization of gate-all-around (GAA) Si nanowire devices

© 2015 IEEE. In CMOS scaling roadmap, gate-all-around (GAA) nanowire (NW) is a promising candidate in sub-10nm nodes. However, newly introduced process options in GAA NW technologies can result in significant impacts on intrinsic ESD performance. In this work, ESD protection devices in GAA NW architecture are studied and the corresponding 3D TCAD simulations bring an in-depth understanding.

ISBN:9781467398930

Publication year:2015

BOF-keylabel:yes

IOF-keylabel:yes

Authors from:Government, Higher Education