On the Characterization and Separation of Trapping and Ferroelectric Behavior in HfZrO FET

OAPA N-channel FETs with ferroelectric (FE) HfZrO gate oxide are fabricated, showing steep subthreshold slope under certain conditions. Possible origins of ID-VG hysteresis, the hysteresis vs. subthreshold slope tradeoff, dependence on the bias voltage and temperature and the competition between trapping and FE behavior are reported and discussed. A band of active traps in the ferroelectric layer responsible for charge trapping during device operation is characterized. Transient ID-VG measurements are introduced to facilitate differentiating between trapping and FE behavior during subthreshold slope measurements.

Publication year:2019

BOF-keylabel:yes

IOF-keylabel:yes

BOF-publication weight:1

CSS-citation score:2

Authors:International

Authors from:Government, Higher Education

Accessibility:Open