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Publication
A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS
Journal Contribution - Journal Article
Journal: IEEE Journal of Solid-State Circuits
ISSN: 0018-9200
Issue: 6
Volume: 55
Pages: 1553 - 1564
Publication year:2020
BOF-keylabel:yes
IOF-keylabel:yes
BOF-publication weight:3
CSS-citation score:2
Authors from:Private, Higher Education
Accessibility:Closed