High-Speed, High-Resolution CMOS Analog-to-Digital Converters

The continuous need for higher data rates and low power dissipation for next-generation communication standards calls for innovation in the design of extremely high-speed analog-to-digital converters (ADCs), exceeding 10 GS/s, while maintaining a medium-to-high resolution. Although complex time interleaving ADCs are a partial solution for this demand, the ADC analog front-end remains a speed bottleneck under power constraints. Moreover, even with careful layout, a time interleaved converter cannot easily overcome fundamental performance limits posed by resolution degradation in the presence of sampling clock jitter. In this dissertation, we aim to precisely identify and solve the bottlenecks that challenge the envisioned high-speed ADCs by research of novel ADC subcircuits and systems. We must ensure that future ADCs can scale along with the progress made in digital integrated circuit design and will correspondingly be designing and taping out the resulting proposals in modern silicon process technologies.