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A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv-step

Book Contribution - Book Chapter Conference Contribution

© 2019 IEEE. Technology scaling has been very beneficial for digital circuits both in terms of speed and power. Traditional analog techniques however are challenged by the ever-decreasing supply voltages. Highly digital VCO-based ADCs are able to benefit directly from improved digital performance [1]; however, the resolution and sampling rate of state-of-the-art VCO-based designs are insufficient for most applications. This paper presents a faster and more efficient VCO-based ADC architecture based on an improved high-speed, low-power ring oscillator and an asynchronous counting strategy. The architecture is 8× time-interleaved and combined with on-chip calibration. The design is implemented in 28nm CMOS and achieves 45.2dB SNDR (7.2 ENOB) near Nyquist at 5GS/s while consuming only 22.7mW, resulting in a Walden FOM of 30.5fJ/conv-step. The core area is only 0.023mm 2 . These results demonstrate that VCO-based ADCs are a viable choice for next-generation Ethernet and high-speed wireless communication.
Book: 2019 IEEE International Solid-State Circuits Conference Digest of Technical Papers
Pages: 328 - 330
Number of pages: 3
ISBN:9781538685310
Publication year:2019
BOF-keylabel:yes
IOF-keylabel:yes
Authors from:Higher Education
Accessibility:Open