An energy-efficient voltage-time hybrid ADC with high linearity and PVT insensitivity

Analog-to-Digital Converters (ADCs) play an important role in mixed-signal integrated circuits. An ADC converts analog signals to digital signals which can be processed by Digital Signal Processors (DSPs). As the processing speed increases, the performance of the ADC should meet more stringent requirements, such as high speed, high resolution, low power, good PVT stability, etc. Although some mature topologies have been implemented for many years, for example, Successive Approximation Register (SAR) ADC, most of them process signals in the voltage domain. However, as technology scales and the supply voltage drops, it is challenging to design a voltage-domain ADC without deteriorating signal-to-noise ratio (SNR). In order to solve the design difficulties imposed by digital-driven technologies, time-domain conversion has drawn increasing attention. Recently, Time-to-Digital Converters (TDCs) have become important in mixed-signal circuits, such as all-digital PLLs/DLLs and time-domain ADCs, thanks to their scaling-friendly characteristic at low supply voltages. The least significant bit (LSB) step of time-domain ADCs can be as small as several to several tens of picoseconds, which is more suitable for high-resolution applications than that of voltage-domain ADCs. On the other hand, voltage-domain ADCs still have advantages over time-domain ADCs. For example, a SAR ADC operates energy efficiently at moderate resolution and speed. Therefore, it is attractive to merge the advantages of voltage-domain and time-domain ADCs to achieve large-swing signal operation and energy efficiency of the voltage domain topology and high resolution of the time domain operation. Moreover, the traditional one-stage ADC limits the potential of breaking the trade-off between resolution and speed. Nevertheless, the two-stage or pipelined structure can maintain high-resolution while operating in a high-speed range. The goal of this PhD project is to investigate and develop novel ADC architectures that push the boundaries of the state-of-the-art at the resolution and speed frontiers. Also, several prototype ADCs will be designed, implemented, taped-out, and measured to verify the real-world performance of the new topologies. The research results will be published at top conferences (ISSCC, VLSI, ASSCC, ESSCIRC, CICC) and in top journals (JSSC).