Design and digital calibration of high‐ performance continuous‐time Delta‐Sigma ADCs

The ultimate pursuit of communication evolution is higher data rate and wider bandwidth, which makes the ADC design in the receiver a challenge. Among all ADC architectures, Continuous‐Time Delta‐Sigma Analog‐to‐Digital Converters (CT-DS ADCs) are widely used in wireless and wireline communications, for their intrinsic anti‐aliasing, easy‐driven resistive input, relatively good power efficiency and high reconfigurability. In high-speed CT-DS ADCs, the errors (including static and dynamic errors) of the front-end feedback DAC become the bottleneck that limits its performance. Previous work mainly focused on how to reduce or eliminate the static errors, and there is little research on dynamic errors that have become non-negligible in high-speed ADCs. Some techniques have been proposed to reduce dynamic errors, but all adopt analog compensation methods that require additional compensation circuits, which finally limits the compensation accuracy. This proposal mainly focuses on the design of high-performance CT-DS ADCs, which uses all-digital or more advanced analog-digital hybrid methods to calibrate the static and dynamic errors of feedback DACs. This design is expected to achieve a SNDR greater than 12bit and considerable power efficiency under a higher bandwidth (≥100MHz).