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Project

Dielectric reliability in 3-D highly scaled interconnects

To further increase the transistors and interconnects densities, several 3-D integration technologies have been adopted by the industry. Among them, pad-to-pad hybrid bonding and Through Silicon Vias (TSV) connections represent the most promising approaches. Hybrid bonding is achieved when copper pads patterned in the outer interconnect layers of two wafers are stacked together. Due to the non-equal pad sizes of the top and bottom wafers, the resulting bonding interface consists of a dielectric-to-dielectric interface, a metal-to-metal interface and a metal-to-dielectric interface, hence the name hybrid-bonding. A TSV consists of a vertical conductor, usually copper, entirely crossing the Si substrate of the stacked dies. It provides an electrical connection between the two faces of a wafer, thus enabling to stack chips upon each other. More recently, nano-TSVs have been proposed to allow the processing of Back-Side Power Delivery Networks (BS-PDN). In this technology, the routing of the power delivery interconnects is performed below the transistors using buried power rails reducing the design pressure for the front side interconnects, ultimately resulting in higher transistor densities. In each of these cases, dielectric materials play a crucial role. While low-k dielectrics are used to isolate electrically the metal interconnects from the silicon substrate, high-k materials are integrated in decoupling capacitors. To guarantee reliable technologies and products, a perfect electrical isolation between adjacent hybrid bonding pads or between a TSV and the substrate must be guaranteed. In addition, the migration of metal ions in the silicon substrate must be avoided. Similarly, a low leakage is expected for decoupling capacitors. Unfortunately, the continuous demand for higher interconnect densities drives pads and TSVs dimensions far in the submicron range, resulting in serious reliability concerns. The aim of this PhD is to understand the degradation mechanisms in dielectrics under electrical stress to help identifying possible mitigation strategies.

Date:19 Sep 2022 →  Today
Keywords:Dielectric reliability
Disciplines:Semiconductor devices, nanoelectronics and technology
Project type:PhD project