Method of patterning target layer

The disclosed technology generally relates to patterning structures in semiconductor fabrication, and more particularly to patterning structures using mask structures having bridged lines. In one aspect, a method for patterning a target layer comprises: forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines, filling the gaps with a sacrificial material, forming a hole by removing the sacrificial material along a portion of one of the gaps, the hole extending across the gap and exposing a surface portion of the target layer and sidewall surface portions of material lines on opposite sides of the one gap, performing a selective deposition process adapted to grow a fill material selectively on the one or more surface portions inside the hole, thereby forming a block mask extending across the gap, removing, selectively to the material lines and the block mask, the sacrificial material from the target layer to expose the gaps, the one gap being interrupted in the longitudinal direction by the block mask, and transferring a pattern including the material lines and the block mask into the target layer.

Patent Publication Number: US10672655

Year filing: 2020

Year approval: 2020

Year publication: 2020

Status: Assigned

Technology domains: Semiconductors

Validated for IOF-key: Yes

Attributed to: Associatie KULeuven