Processor design for latency-critical and latency-scalable applications
In the recent years, most of the optimizations in embedded deep learning processor design has been concentrated to make the processors more power and resource efficient. Energy-efficiency is an important aspect for the processor because of its use in battery-operated applications. However, when considering energy-efficiency, the performance of the processor is put into back seat. Reducing the processors computation capability decreases the power consumption but increases the latency of operations. In applications such as drones, VR, AR, etc., where timely response of the processor is one of the primary requirement, reducing the computational capability produces detrimental effects. In this research work, we aim to design a deep learning processor that can adapt to latency requirements of the application and at the same time providing a considerable energy-efficiency. The mechanism for achieving a latency-critical and latency-scalable processor architecture will be explored and a suitable design will be implemented.