Radiation tolerant CMOS optical and wireline communication circuits

The next generation of integrated systems on chips (SoCs) for space applications demand a large scale of integration, combined with ever increasing susceptibility to single-event effects in nanoscale CMOS technologies such as 65 nm and 28 nm nodes and 22 nm FDSOI nodes. Many of these SoCs require the generation of clocks, frequencies or an exchange of serial data in the chip. In clock- or frequency synthesizers, a PLL is used to generate a high-speed clock from a low- medium frequency reference. In data link systems, a high-speed clock drives a serializer while a clock-data recovery (CDR) circuit recovers a clock from a serial data-stream. In practice, the design of high-speed PLLs/CDRs is a challenging task. Such a design typically takes between 1 year to 3 years for production-ready IP cores. In this project, a novel radiation hardened All-Digital PLL/Clock-Data Recovery (ADPLL) architecture will be developed that can support an ultra-wide range of applications and is highly flexible with respect to the input and output frequencies (1 MHz – 5 GHz). The project targets ultra-low integrated phase noise (<0.3 ps) and up to 2.5 Gbps serial clock recovery rates. The circuits will be designed and prototyped in a commercial 65 nm CMOS technology that has been highly embraced by the space community as an industry-standard ASIC technology. Due to its highly digital architecture, the circuits will allow to easily port them towards more energy efficient CMOS technologies. ADPLLs differ from traditional charge-pump PLLs (CPPLL) by implementing the loop filter in the digital domain. They use a digitally controlled oscillator (DCO) instead of a voltage controlled oscillator (VCO). These circuits are highly digital and benefit from recent improvements of digital nanoscale technologies. The goal of this project is the development of an ADPLL core with a wide-range programmable output frequency to support different applications. The ADPLL will be fully protected from single-event upsets (SEU) with Triple-Modular Redundancy (TMR) in the digital cores where necessary to provide an SEU tolerance beyond 120 MeV.cm²/mg. Since the analog loop filters are replaced with their digital counterparts, the entire loop can be protected with redundancy. One task in this research project is to investigate the required level of redundancy, since this will increase the power consumption and area. A flexible and programmable loop control is foreseen that can be tuned to serve different applications and which is insensitive to ionizing radiation effects. The major challenges in that are tackles in this PhD project are: 1. Studying the effects of SEU errors in the digital control signals and the required level of protection that is required. 2. Development of a radhard oversampled GRO (Gated Ring Oscillator) which is a 1st order noise shaped system an which single-event sensitivity is unknown. And 3. Study of the architectural requirements that are common between the vast majority of the targeted applications and providing the most amount of support in a single IP core. Several minor challenges such as DCO hardening, automatic gain calibration and reliable lock monitoring will be included in this project as well. A dedicated IP core will be designed and delivered at the end of this project that can be implemented on a larger SoC or detector readout circuit with a flexible configuration to meet different applications. The targeted circuit is extremely insensitive to process variations and lifetime degradation due to its digital behavior since the loop dynamics do not depend anymore on analog capacitors or currents. Therefore, the targeted production costs and IP integration complexity is much smaller compared to its analog counterparts. The final goal of this project is a general, customizable PLL/CDR IP block that addresses the needs of various applications to reduce the design time and design effort by centralizing the PLL/CDR expertise in one project. The goal is to present an IP core that is open and highly adjustable to meet the needs of different systems.