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Reconfigurable Neural Network architectures, circuits, transistors (recoNNact)

Embedded neural networks become more and more important, as they offer superior task performance compared to many traditional algorithms. However they are much more compute heavy than the traditional algorithms, putting a large burden on the power envelope of the embedded platform. This trend is also observed for next generation hearing aids, requiring advanced low-power embedded audio machine learning processing, including improved denoising capabilities in complex acoustic scenes. The general purpose of the project is to conceive, develop and validate a processor and memory architecture capable of executing dynamically-sparse neural networks, by enabling the exploitation of dynamically adapting supply voltage, clock speed, processor configuration and memory configuration in function of the current network workloads and/or detected audio scene. The largest gains in energy efficiency are expected to come from the cross abstraction level optimization of the processor and memory architecture in combination with built-in timing monitors. The project itself will be a close collaboration between the MICAS research division and NXP Product Line Personal Health (PL PH), that is currently focusing on IC developments dedicated to hearing aids.

Date:11 Sep 2021 →  Today
Keywords:neural networks, low power, reconfigurable memory architecture, reconfigurable hardware, in-situ timing monitoring, integrated circuits
Disciplines:Digital integrated circuits
Project type:PhD project