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Strength and Reliability Characterization of Multi-Level Back-End-of-Line under Chip Package Interaction Loading

With the ever increasing demands for improved performance of ICs, new reliability challenges are arising with the increasing complexity of the interconnect layer, which consists not only of reduction of dimensions, but also the introduction of new materials. One of the main goals of the semiconductor industry is to increase the speed of ICs (both Front-End-Of-Line and Back-End-Of-Line), by reducing the RC delay. While the downscaling increased the performance in terms of decreasing the gate delay, the delay of the interconnect layer keeps increasing, significantly hampering the performance of ICs. In order to circumvent that and reduce the RC delay, ultra low-k dielectrics, with low dielectric constant, are introduced in BEOL (Back-end-of-line). However, the electrical improvement that comes with the introduction of low-k dielectrics, also comes at cost of decreased mechanical integrity. 

This is critical, as the BEOL is subjected to high thermo-mechanical stresses induced by the different coefficients of thermal expansion (CTE) between the silicon die containing Cu/low-k interconnects and the package during different processing steps, which can lead to a number of failures in the BEOL.

In this work, a framework for solving CPI related BEOL failures is presented. The framework consists of several different steps. As a first step, a dedicated CPI test vehicle (or test chip), named PTCR, is designed, consisting of several different CPI sensors, which are positioned at different locations in the chip, with a purpose of detecting failures during packaging process and reliability testing. The test chip consists of different BEOL configurations, with different metal and airgap densities, as well as different passivation and stress mitigation modules.

As a second step, a compact analytical model is built, which is used to evaluate the impact of different BEOL designs (metal density, airgap density, passivation thickness, etc., which we refer to as design variables) on the mechanical properties of the BEOL. The purpose of the analytical analysis is to help increase the understanding of the design variable influence at the fundamental level, where we see a significant increase in BEOL stiffness and fracture toughness with the increase of via density and low-k stiffness. Following an analytical analysis, a more detailed numerical analysis using FEM (Finite Element Method) simulations is performed, focusing on metal via peel stresses. The models are used to develop response surfaces for different vias, which allow for easy identification of critical design variables. There we observe a reduction in via stresses by up 20% with the increase in via density. Additionally, a decision making technique is introduced with a purpose of identifying the best BEOL design, based on predefined criteria, which in this particular case are via stresses.

The first experimental validation step consist of wafer level nano-indentation test. The nano-indentation test is a simple, fast, and repeatable technique that allows for determining the mechanical properties of single materials and BEOL stacks at the early stages of fabrication. Using nano-indentation technique we determined the influence of via and airgap density on the mechanical stability of the BEOL, by measuring the crack length after the nano-indentation test. The via density was proved to have significant influence on the crack length, where an increase in average via density significantly reduces the crack length. On the other hand, the change in airgap density has no influence on the crack length in the BEOL. In order to complement nano-indentation tests, a number of wafer level shear tests have been performed on industry 28 nm node devices. Test have shown that the changing loading conditions (in the terms of lower shear speed) can completely alter the failure modes, from bump failure to BEOL failure. The change in failure mode is accompanied in the change of required lateral force, where the BEOL failure required lower force which will result in a failure. Two different failure modes also showed a different crack pattern in the passivation.

Following a wafer level assessment, a two-step package level validation is performed. In the first step, a pre- and post- packaging comparison of PTCR CPI test structures is made. The analysis have shown that once via density drops below 1% in one of the BEOL layers, there is an increased probability of failure. Additionally, a reduction in average via density will increase the probably of crack propagating in multiple BEOL layers by approx. 30%. In the second step, a thermal cycling reliability test is preformed, which was used to assess the influence of via density and different passivation modules. As in the previous tests, an increase in average via density resulted in a reduced number of failures, nearly halving them in the case of thin passivation module. Changing the passivation thickness also has a significant impact on the number of BEOL failures, where the thinner passivation reduces the number of failures compared to the thick passivation, due to lower residual stresses. BEOL failures can further be reduced by employing different stress mitigation strategies. However, care needs to be taken not to compromise chip-to-package interconnect integrity. In particular, adding a soft buffer layer will reduce a number of BEOL failures, however at the cost of increased number of failures at the bump level, where the total failure percentage can reach 25% after 2000 thermal cycles.

Finally, package level failure analysis is performed. In the first case, cracks are visualized in the BEOL after package cross-sectioning, followed by the SEM inspection. A second technique is also introduced, where the full BEOL has been exposed with a combination of package decapsulation, Si thinning, and Si etching. In both cases the majority of cracks were present in the weak BEOL layers, employing porous low-k dielectric.

We can conclude that with a presented framework it is possible to evaluate the influence of a wide range of design variables at different design and fabrication stages, and implement different solutions for increasing the mechanical integrity of the BEOL under CPI loading.

Date:4 Mar 2013 →  12 Dec 2017
Keywords:Back-End-Of-Line, Chip-Package Interaction, Mechanical reliability
Disciplines:Metallurgical engineering, Ceramic and glass materials, Materials science and engineering, Semiconductor materials, Other materials engineering
Project type:PhD project