Circuit-Technology Co-optimization of SRAM Design in Advanced CMOS Nodes

The impressive growth of the semiconductor industry in the past few decades has been driven by CMOS technology scaling. Miniaturizing the CMOS devices provides larger integration density, higher performance while lower the power consumption. However, as CMOS scales down to node N5 and beyond, gate length scaling becomes increasingly difficult if not impossible. Furthermore, the resistance of local interconnect in advanced nodes becomes the main bottleneck in extracting performance benefit from CMOS technology scaling. Achieving power, performance, and area gain from CMOS technology scaling as predicted by Moore’s law thus requires innovation in technology, device architecture, circuit, and system design. 3D integration has been perceived as the promising candidate for extending Moore’s law without scaling the critical device/interconnect dimensions. The primary objectives are to come up with standard cell architecture, floor-planning, and efficient interconnect architecture to support semiconductor scaling using 3D integration approach.