Thermal gradients impacting reliability in nano-wires, 3D-TSVs and heaters
Recent developments in advanced on-chip and 3D-TSV interconnects lead to the introduction of thermal gradients during chip operation and reliability testing. Also, metal or Si-heaters for Si photonics applications require high currents leading to thermal gradients. Interconnects reliability is classically tested using constant current stresses at elevated temperatures. The interconnect failure mechanism triggered by these tests is called electromigration and the lifetime model used in this case is the classical Black’s law. Unfortunately, this model is only valid if the Joule heating induced by the stress current in the metal line is limited. If this condition is not fulfilled, the parameters extracted with this model are meaningless. While electromigration tests on nowadays interconnects fulfill the absence of Joule heating requirement, this is not the case in advanced on-chip and 3D-TSV interconnects. Obviously, for metal or Si-heaters for Si photonics thermal gradients need to be properly considered during reliability testing as well. As a result, a new approach to electromigration testing is needed. The goal of this PhD topic is to investigate and study the reliability of advanced interconnects when thermal gradients are present. The study should lead to the following achievements: • Gaining a deeper understanding of the electromigration failure mechanism when a thermal gradient is present in the line under test; • Building a reliability model calibrated and validated with experimental data measured on suitable test structures, which would allow lifetime predictions in function of the line dimensions and in presence of a thermal gradient; • Identifying by the model the suitable line dimensions, stress gradient and thermal gradient properties which guarantees the respect of the lifetime specs for the interconnections.