Time-based Biomedical Readout Circuits in Low-Voltage Nanometer CMOS

Personalized healthcare applications require low-cost sensor readouts that have a small form factor and can acquire multiple signal modalities. This requires sensor circuits that are accurate, have extensive information processing capabilities, while being able to operate with low supply voltages. A significant challenge in achieving this requirement is designing a power- and area-efficient analog front-end (AFE) in a low-voltage-supply and/or a small-scale CMOS technology.

It is shown in this thesis that one the main reasons for this to be challenging is the limited voltage headroom, due to the low voltage supply. Other challenges that exist arise from scaling down the transistor size, resulting in an increase in flicker noise, an increase in gate leakage current, a decrease in the intrinsic gain of the transistor and the fact that the area of on-chip passives does not scale down with technology. Each of these challenges and their existing solutions are discussed in detail in this thesis.

The central goal of this thesis is to show that the larger dynamic range available in the time domain can be utilized to overcome the problem of the limited voltage headroom and thereby to design power- and area-efficient analog circuits. Towards this end, a key voltage-to-time converter block: a time-based loop is proposed. It essentially consists of a comparator with a 1-bit DAC and an integrator in the feedback. While this architecture has been utilized earlier in applications such as ADCs, communications and power regulation, it has never been analysed and implemented specifically for biomedical applications. To do so, in this thesis, we develop small-signal equations for the gain, the loop gain and the noise performance of the loop. These are then used to optimize the design and consequently, allow us to obtain significant benefits w.r.t. state-of-the-art designs.

To verify the feasibility of the proposed concept, two prototypes for ECG readout, each targeting a different application, are designed, implemented and measured. In the first implementation, a time-based instrumentation amplifier (IA) is designed in 180 nm CMOS technology for a prototype ECG readout application. It can operate at 0.35 V, while consuming a power of 210 nW. For traditional voltage-domain circuits with insufficient voltage headroom, the design of a power-efficient and high-gain opamp is one of the main challenges at functioning at such a low voltage supply. In this thesis, however, thanks to the proposed time-based operation, the measured results of the time-based IA show an improvement of > 3x in power consumption for a similar gain w.r.t the state of the art. This design is relevant for readouts required in long-lifetime sensor applications.

In the second implementation, a time-based analog front-end (AFE) for ECG readout is designed in 40 nm CMOS technology that can operate at 0.6 V, while consuming a power of 3.3 µW and a silicon area of 0.015 mm2. The circuit can handle a 40 mVpp input AC signal and + 150 mV DC-electrode offset. In a small-scale CMOS technology, such as 40 nm CMOS, existing voltage-based AFE design techniques face a challenging trade-off between the area consumption, the power consumption and the dynamic range. In this implementation, the time-domain operation enables us to overcome the limited voltage headroom. It also helps us to overcome the problem of the reduced intrinsic gain by enabling the use of scalable blocks such as dynamic comparators. Flicker noise is reduced by using the chopping technique. The measurement results show an improvement of > 5x dynamic range w.r.t the state of the art with similar area and power consumption.

These prototype designs not only enable low-cost, low-power sensor solutions for personalized healthcare applications, but also open further avenues for analog design in for an ultra-low supply voltage and/or in a small-scale CMOS technology.