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Project
Towards zero-power sensor interfaces for future cyber-physical systems.
A new electronic revolution is arising: the smart environment. This means that sensors and sensor systems are becoming ever more important in todays society, and at the same time are getting more and more networked. If all this will be realized, one can speak of real Cyber-Physical Systems and the Internet of Things. There are however still obstacles that need to be tackled for this to become a reality.
In order to be able to massively deploy these systems, three main challenges at the hardware level have to be addressed. The first is the power consumption and the corresponding energy consumption. Since these systems need to operate autonomously, only limited energy is available through energy harvesting. Secondly, these systems need to be as robust as possible, because they need to be deployed in all kinds of harsh environments. And thirdly, decreasing the cost is a major challenge in order to be able to deploy these systems at a large scale. Therefore, integration and miniaturization are necessary to meet this requirement.
In the past, the scaling of Si CMOS technology has offered the solution to get more for less. However, there has come an end to happy scaling, and traditional amplitude-based sensor interfaces suffer from the decreased voltage headroom in nanometer CMOS technologies. Additionally, these analog sensor interfaces do not really benefit from scaling in terms of chip area reduction. Therefore, this thesis proposes to process the sensor information inthe time domain, as time-based implementations can be highly digital, which means that they can benefit from scaling in terms of chip area reduction and increasing timing resolution. Furthermore, ultra-low-voltage design becomes feasible. However, an analysis of the fundamental difference between amplitude- and time-based processing in terms of energy efficiency shows that the fundamental thermal-noise-limited energy efficiencyis mainly sensor-dependent. The drive to implement time-based sensor interfaces is thus not based on improving the energy efficiency, but rather on the benefits of the highly-digitalature and the related area/cost scaling.
This thesis presents, analyzes and validates through chipimplementations one type of such time-based sensor interfaces: the Bang-Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. Basically, the conversion mechanism is based on frequency modulation and demodulation. The proposed highly-digital BBPLL SDC offers the possibility of low-voltage design, small chip area, and low power consumption possibilities due to its digital nature. Additionally, the sensor interface is very robust, as it can suppress common-mode variations such as supply-voltage and temperature variations. It also resembles a modulator, hence benefiting from noise shaping and oversampling. The BBPLL SDC is thoroughly analyzed through analytical analysis and simulations. A complete state-variable-based Matlab model is implemented with all its nonidealities, so that conclusions as close as possible to reality are drawn. The phase noise ofthe oscillators is the key in designing energy-efficient or high-resolution sensor interfaces.
The promising BBPLL SDC architecture is validated through several chip implementations. In a first implementation part, three chip implementations are done in silicon CMOS technology. The first design focuses on the direct conversion of sensor information to the time/frequency domain for capacitive sensors by means of a capacitance-controlled oscillator. In this way, power-consuming analog conditioning circuits can be avoided. In addition, the design shows the feasibility of integrating external (MEMS) sensors in on-chip oscillators. The second design is a BBPLL SDC for resistive sensors. It aims to improve the PSRR of traditional Wheatstone-bridge interfaces and shows the robustness of the architecture. It combines in one circuit an improved resilience towards supply-voltage and temperature variations, with low powerconsumption and good energy efficiency. The two previous implementations are done in a 130-nm CMOS technology. The third design implementation shows the low-voltage and ultra-low-power possibilities of the BBPLL SDC, by implementing it in a 28-nm CMOS technology with ultra-low-VT transistors. It is implemented with inverters, D-flipflops and transmission gates only. Furthermore, it presents a technique to improve the linearity of the sensor-to-digital conversion.
In the second implementationpart, two chip implementations are presented in carbon nanotube (CNT) technology. This work has been done in collaboration with the groups of prof. Mitra and prof. Wong of Stanford University and all the fabricationhas been done at the Stanford Nanofabrication Facility. CNT technology is a promising technology to further reduce the energy consumption in electronics, as it is projected that it can achieve an order of magnitude improvement in energy-delay product compared to Si CMOS at highly-scaledtechnology nodes. In addition, CNTs are excellent candidates to be implemented as sensors, due to their large surface-area-to-volume ratio. This means that CNT technology is an interesting technology in the search for improved energy efficiency in sensors and sensor interfaces. In the first implementation, a BBPLL SDC for capacitive sensors is implemented entirely using CNFETs and shows that the implementation of larger systemsin CNT technology is feasible. The design has been fabricated in a 1-μm CNT pMOS-only technology of Stanford University. This design implementation is the first-ever sensor interface circuit implemented entirely using CNFETs. The second design in CNT technology is implemented in a 32-nm scaled CNT technology and shows the feasibility of scaling in CNT technology in a VLSI-compatible manner. It comprises both a CNFET-based sensor and a time-based sensor interface circuit on a single die. This might be the first step towards future extremely-energy-efficient integrated smart sensor systems.
In order to be able to massively deploy these systems, three main challenges at the hardware level have to be addressed. The first is the power consumption and the corresponding energy consumption. Since these systems need to operate autonomously, only limited energy is available through energy harvesting. Secondly, these systems need to be as robust as possible, because they need to be deployed in all kinds of harsh environments. And thirdly, decreasing the cost is a major challenge in order to be able to deploy these systems at a large scale. Therefore, integration and miniaturization are necessary to meet this requirement.
In the past, the scaling of Si CMOS technology has offered the solution to get more for less. However, there has come an end to happy scaling, and traditional amplitude-based sensor interfaces suffer from the decreased voltage headroom in nanometer CMOS technologies. Additionally, these analog sensor interfaces do not really benefit from scaling in terms of chip area reduction. Therefore, this thesis proposes to process the sensor information inthe time domain, as time-based implementations can be highly digital, which means that they can benefit from scaling in terms of chip area reduction and increasing timing resolution. Furthermore, ultra-low-voltage design becomes feasible. However, an analysis of the fundamental difference between amplitude- and time-based processing in terms of energy efficiency shows that the fundamental thermal-noise-limited energy efficiencyis mainly sensor-dependent. The drive to implement time-based sensor interfaces is thus not based on improving the energy efficiency, but rather on the benefits of the highly-digitalature and the related area/cost scaling.
This thesis presents, analyzes and validates through chipimplementations one type of such time-based sensor interfaces: the Bang-Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. Basically, the conversion mechanism is based on frequency modulation and demodulation. The proposed highly-digital BBPLL SDC offers the possibility of low-voltage design, small chip area, and low power consumption possibilities due to its digital nature. Additionally, the sensor interface is very robust, as it can suppress common-mode variations such as supply-voltage and temperature variations. It also resembles a modulator, hence benefiting from noise shaping and oversampling. The BBPLL SDC is thoroughly analyzed through analytical analysis and simulations. A complete state-variable-based Matlab model is implemented with all its nonidealities, so that conclusions as close as possible to reality are drawn. The phase noise ofthe oscillators is the key in designing energy-efficient or high-resolution sensor interfaces.
The promising BBPLL SDC architecture is validated through several chip implementations. In a first implementation part, three chip implementations are done in silicon CMOS technology. The first design focuses on the direct conversion of sensor information to the time/frequency domain for capacitive sensors by means of a capacitance-controlled oscillator. In this way, power-consuming analog conditioning circuits can be avoided. In addition, the design shows the feasibility of integrating external (MEMS) sensors in on-chip oscillators. The second design is a BBPLL SDC for resistive sensors. It aims to improve the PSRR of traditional Wheatstone-bridge interfaces and shows the robustness of the architecture. It combines in one circuit an improved resilience towards supply-voltage and temperature variations, with low powerconsumption and good energy efficiency. The two previous implementations are done in a 130-nm CMOS technology. The third design implementation shows the low-voltage and ultra-low-power possibilities of the BBPLL SDC, by implementing it in a 28-nm CMOS technology with ultra-low-VT transistors. It is implemented with inverters, D-flipflops and transmission gates only. Furthermore, it presents a technique to improve the linearity of the sensor-to-digital conversion.
In the second implementationpart, two chip implementations are presented in carbon nanotube (CNT) technology. This work has been done in collaboration with the groups of prof. Mitra and prof. Wong of Stanford University and all the fabricationhas been done at the Stanford Nanofabrication Facility. CNT technology is a promising technology to further reduce the energy consumption in electronics, as it is projected that it can achieve an order of magnitude improvement in energy-delay product compared to Si CMOS at highly-scaledtechnology nodes. In addition, CNTs are excellent candidates to be implemented as sensors, due to their large surface-area-to-volume ratio. This means that CNT technology is an interesting technology in the search for improved energy efficiency in sensors and sensor interfaces. In the first implementation, a BBPLL SDC for capacitive sensors is implemented entirely using CNFETs and shows that the implementation of larger systemsin CNT technology is feasible. The design has been fabricated in a 1-μm CNT pMOS-only technology of Stanford University. This design implementation is the first-ever sensor interface circuit implemented entirely using CNFETs. The second design in CNT technology is implemented in a 32-nm scaled CNT technology and shows the feasibility of scaling in CNT technology in a VLSI-compatible manner. It comprises both a CNFET-based sensor and a time-based sensor interface circuit on a single die. This might be the first step towards future extremely-energy-efficient integrated smart sensor systems.
Date:1 Oct 2010 → 18 Nov 2014
Keywords:Sensor interfaces, Cyber-physical systems, (ultra) low power, Wireless sensor networks
Disciplines:Nanotechnology, Design theories and methods
Project type:PhD project