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Ultra low voltage variation resilient digital circuit design

In the proposed research we will further investigate ultra low power digital circuit techniques. The focus will be on in-situ timing detection with automatic error correction and/or prevention for further power reduction in digital circuits. It also entails the verification of the results with silicon prototypes in advanced CMOS technologies. The techniques that will be studied and further developed should be compatible with the standard digital design flows.

Date:7 Nov 2018 →  Today
Keywords:Ultra-low energy, Near-subthreshold digital design, In-situ timing detection
Disciplines:Nanotechnology, Design theories and methods, Sensors, biosensors and smart sensors, Other electrical and electronic engineering
Project type:PhD project