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A 0.5mm2 power scalable 0.5-3.8 GHz CMOS DT-SDR receiver with 2nd order RF band-pass sampler

Journal Contribution - Journal Article

A highly flexible receiver chain based on RF-sampling and discrete-time signal processing in the charge domain for SDR applications is presented. A compact switched-inductor variable-gain front-end provides multiband low noise amplification and RF-selectivity with reduced area penalties. Strong selectivity at RF was obtained through a novel discrete-time decimating bandpass filter with triangular weighted filter taps. Decimation filters with programmable number of taps offer flexible rate decimation. A power scalable discrete-time baseband filter was implemented in-order to minimize static power consumption. The 90-nm digital CMOS implementation achieves a noise figure of 5.1 dB, a variable gain range of more than 60 dB with approx. 1 dBm IIP3 and 50 dBm IIP2. This is achieved for power figures competitive with dedicated solutions. The receiver, frequency synthesizer excluded, occupies only 0.5 mm
Journal: IEEE Journal of Solid-State Circuits
ISSN: 0018-9200
Issue: 11
Volume: 45
Pages: 2375-2387
Publication year:2010
Keywords:Band-pass sampling, discrete-time signal processing, multiband receiver, programmable charge domain filter, RF-sampling, software-defined radio (SDR), switched inductor, switched OPAMP
  • ORCID: /0000-0001-7582-7246/work/69374155
  • ORCID: /0000-0003-2738-7914/work/69212164
  • Scopus Id: 78049313307