Minimum Power in Analog Amplifying Blocks: Presenting a Design Procedure

© 2015 IEEE. Power consumption is a result of high speed and low noise requirements, and it can be minimized, provided proper operating points are selected for the input transistors. This is achieved by adopting a design procedure in which BSIM6/EKV model parameters are used to derive the gain and speed characteristics in asymptotic form. All three regions of operation i.e., strong and weak inversion and velocity saturation, are included. This design procedure is developed for channel lengths down to 5 nm. It is shown that inversion coefficients must be used around unity or (L/20 nm)2, depending on the actual channel length.

Publication year:2015