< Back to previous page

Publication

Multirate Cascaded Discrete-Time Lowpass Delta Sigma Modulator for GSM/Bluetooth/UMTS

Journal Contribution - Journal Article

This paper shows that multirate processing in a cascaded discrete-time 16 modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time 16 modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded 16 modulator enables the power efficient implementation of multiple communication standards. The advantages of multirate cascaded 16 modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time 16 modulator. A 2-1 multirate low-pass cascade, with a sa
Journal: IEEE Journal of Solid-State Circuits
ISSN: 0018-9200
Issue: 6
Volume: 45
Pages: 1198-1208
Publication year:2010
Keywords:Cascade, CMOS, delta sigma modulation, multi-mode, multirate, sigma delta modulation
  • ORCID: /0000-0001-7582-7246/work/69374287
  • ORCID: /0000-0003-2738-7914/work/69212327
  • Scopus Id: 77953238965