POWER-AWARE EVALUATION FLOW FOR DIGITAL DECIMATION FILTER ARCHITECTURES FOR HIGH-SPEED ADCS

The raising cost of the latest technology nodes as well as the design cost associated has motivated an increasing push for flexible radio implementations. In this context, Sigma-Delta (ΣΔ) ADCs have emerged as a promising alternative to direct conversion. In this work a novel wireless receiver architecture based on an RF bandpass ΣΔ is considered. One of the key blocks of this architecture is the digital decimation filter which needs to run at very high speed. In order to offer competitive power consumption, the implementation of this decimation filter needs to be thoroughly optimized. Considering that many implementation options are possible, this paper presents an early evaluation flow, which still considers relevant implementation details to aid designers in selecting the most optimal implementation option. The flow is shown for a design of a 9-bits ADC targeting 40nm CMOS technology. The power consumption of the optimal implementation option is shown to be below 12.6 mW. ©2009 IEEE.

ISBN:978-1-4244-4334-5

Publication year:2009