< Back to previous page
Technology optimization for high bandwidth density applications on 3D interposer
Book Contribution - Book Chapter Conference Contribution
© 2016 IEEE. 3D interposers are one of just a few ways of making electronic systems faster and more powerful, but their design can be complex. This paper presents a optimization flow to assist the design of silicon interposers with the highest bandwidth density possible. Using the methodology described in this paper, simulations have shown that chip-to-chip links on a silicon interposer can achieve bandwidth densities between 250Gbps/mm and 4.5Tbps/mm depending on a wide range of parameters such as interconnect length, interlayer dielectric (ILD) material and micro-bump pitch.
Book: 2016 6TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC)
Pages: 1 - 6