Researcher
Bao Trong Huynh
- Keywords:Electronics and electrical engineering
- Disciplines:Engineering and technology
Affiliations
- Faculty of Engineering (Faculty)
Member
From20 Aug 2015 → 5 May 2017 - Electronics and Informatics (Department)
Member
From1 Nov 2012 → 31 Oct 2016
Publications
1 - 7 of 7
- Design-technology co-optimization of vertical gate-all-around transistors for the beyond-5nm CMOS generations(2017)
Authors: Bao Trong Huynh, Piet Wambacq
- Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs(2016)
Authors: Bao Trong Huynh, Julien Ryckaert, Sushil Sakhare, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Piet Wambacq
Number of pages: 12 - A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs(2016)
Authors: Bao Trong Huynh, Sushil Sakhare, Julien Ryckaert, Dimitri Yakimets, Aaron Thean, Abdelkarim Mercha, Diederik Verkest, Piet Wambacq
Pages: 643-651 - Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM(2015)
Authors: Bao Trong Huynh, Sushil Sakhare, Julien Ryckaert, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Piet Wambacq
Pages: 1-4Number of pages: 4 - Vertical device architecture for 5nm and beyond: device & circuit implications(2015)
Authors: AV-Y Thean, Dimitri Yakimets, Bao Trong Huynh, P. Schuddinck, Sushil Sakhare, M Garcia Bardon, A. Sibaja-Hernandez, I Ciofi, G. Eneman, A Veloso, et al.
Pages: 26-27 - Lateral versus vertical gate-all-around FETs for beyond 7nm technologies(2014)
Authors: Dmitry Yakimets, Bao Trong Huynh, M Garcia Bardon, Morin Dehan, Nadine Collaert, Abdelkarim Mercha, Zsolt Tokei, Aaron Thean, Diederik Verkest, Kristin De Meyer
Pages: 133-134Number of pages: 2 - Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies(2014)
Authors: Bao Trong Huynh, D Yakimets, Julien Ryckaert, I Ciofi, R Baert, A Veloso, J Boemmels, Nadine Collaert, P Roussel, S Demuynck, et al.
Pages: 102-105Number of pages: 4
Patents
1 - 10 of 10
- Method of fabricating vertical transistor device
- Spin-torque transfer switchable magnetic tunnel junction unit and a memory device
- A bit cell for a static random access memory
- Standard cell for vertical transistors (Inventor)
- Non-volatile SRAM cell using resistive memory elements
- A magnetic tunnel junction unit and a memory device
- Static random access memory device having interconnected stacks of transistors
- A method for defining a channel region in a vertical transistor device
- Method of forming vertical transistor device
- Non-volatile sram cell using resistive memory elements