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Researcher
Filip Tavernier
- Disciplines:Nanotechnology, Sensors, biosensors and smart sensors, Other electrical and electronic engineering, Design theories and methods
Affiliations
- Electronic Circuits and Systems (ECS) (Division)
Member
From1 Aug 2020 → Today - Assiocated Division ESAT-INSYS (INSYS), Integrated Systems (Division)
Member
From1 Aug 2020 → 31 Dec 2008 - Department of Electrical Engineering (ESAT) (Department)
Member
From1 Apr 2006 → 18 Nov 2007 - ESAT - MICAS, Microelectronics and Sensors (Division)
Member
From17 Oct 2005 → 31 Jul 2020
Projects
1 - 10 of 28
- Extreme High Speed ADCFrom12 Mar 2024 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
- High voltage, low power DC-DC convertersFrom13 Oct 2023 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
- Scalable large array nanopore readouts for proteomics and next-generation sequencingFrom2 Oct 2023 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
- Essential Technologies for the Einstein TelescopeFrom1 Jan 2023 → TodayFunding: FWO International research infrastructure (IRI)
- Cryogenic Oscillators and ClocksFrom1 Nov 2022 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
- Cryogenic measurement platforms for quantum technologiesFrom1 May 2022 → TodayFunding: FWO Medium Size Research Infrastructure
- GARLIC: a Generic ARchitecture of a Low-loss Integrated Converter, eliminating Vampire PowerFrom1 Oct 2021 → TodayFunding: IOF - technology validation in lab
- An energy-efficient voltage-time hybrid ADC with high linearity and PVT insensitivityFrom27 Sep 2021 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
- Cryo-CMOS circuits for quantum computingFrom1 Sep 2021 → TodayFunding: FWO fellowships
- High speed, radiation-tolerant optical and wireline communication circuitsFrom29 Jan 2021 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
Publications
51 - 60 of 80
- A 1310/1550nm Fully-Integrated Optical Receiver with Schottky Photodiode and Low-Noise Transimpedance Amplifier in 40nm Bulk CMOS(2018)
Authors: Wouter Diels, Michiel Steyaert, Filip Tavernier
Pages: 242 - 245Number of pages: 4 - A Capacitive DC-DC Converter for Stacked Loads With Wide Range DVS Achieving 98,2% Peak Efficiency in 40nm CMOS(2018)
Authors: Tim Thielemans, Nicolas Butzen, Aki Sarafianos, Michiel Steyaert, Filip Tavernier
Pages: 1 - 4Number of pages: 4 - A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW Single-Channel SAR ADC in 28nm Bulk CMOS(2017)
Authors: Athanasios Ramkaj, Michiel Steyaert, Filip Tavernier
Pages: 167 - 170 - High-gain and power-efficient dynamic amplifier for pipelined SAR ADCs(2017)
Authors: Yifan Lyu, Athanasios Ramkaj, Filip Tavernier
Pages: 1510 - 1511 - A 0.4-3.3 GHz Low-Noise Variable Gain Amplifier with 35 dB tuning range, 4.9 dB NF, and 40 dBm IIP2(2017)
Authors: Filipe Dias Baumgratz, Filip Tavernier
Pages: 9 - 17 - Modelling, design and characterization of Schottky diodes in 28nm bulk CMOS for 850/1310/1550nm fully integrated optical receivers(2017)
Authors: Wouter Diels, Michiel Steyaert, Filip Tavernier
Pages: 224 - 227 - Schottky diodes in 40nm bulk CMOS for 1310nm high-speed optical receivers(2017)
Authors: Wouter Diels, Michiel Steyaert, Filip Tavernier
Pages: 1 - 3 - 10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS(2016)
Authors: Filip Tavernier
Pages: 2502 - 2510 - GBLD10+: a compact low-power 10 Gb/s VCSEL driver IC(2016)
Authors: Filip Tavernier
- When hardware is free, power is expensive! Is integrated power management the solution?(2015)
Authors: Filip Tavernier, Hans Meyvaert, Aki Sarafianos, Nicolas Butzen
Pages: 26 - 34
Patents
1 - 1 of 1
- Light-to-digital converter (Inventor)