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Researcher
Geert Hellings
- Disciplines:Nanotechnology, Design theories and methods
Affiliations
- Assiocated Division ESAT-INSYS (INSYS), Integrated Systems (Division)
Member
From1 Aug 2020 → 31 Dec 2011 - Electronic Circuits and Systems (ECS) (Division)
Member
From1 Aug 2020 → 30 Nov 2011 - Associated Section of ESAT - INSYS, Integrated Systems (Division)
Member
From19 Nov 2007 → 31 Dec 2011 - Department of Electrical Engineering (ESAT) (Department)
Member
From16 Apr 2005 → 18 Nov 2007
Publications
11 - 20 of 74
- System-level ESD protection design using on-wafer characterization and transient simulations(2014)
Authors: Shih-Hung Chen, Geert Hellings, Guido Groeseneken
Pages: 104 - 111 - Improvement on CDM ESD robustness of high-voltage tolerant nLDMOS SCR devices by using differential doped gate(2014)
Authors: Shih-Hung Chen, Geert Hellings, Roman Boschke, Guido Groeseneken
Number of pages: 5 - Kinetic Monte Carlo simulations for dopant diffusion and defects in Si and SiGe(2013)
Authors: Naoto Horiguchi, Taiji Noda, Liesbeth Witters, Jerome Mitard, Erik Rosseel, Geert Hellings, Christa Vrancken, Pierre Eyben, Hugo Bender, Aaron Thean, et al.
Pages: 78 - 83 - Quasi-3D method: time-efficient TCAD and mixed-mode simulations on finFET technologies(2013)
Authors: Geert Hellings, Shih-Hung Chen, Guido Groeseneken
Pages: 8 - Exploring ESD challenges in sub-20-nm bulk FinFET CMOS technology nodes(2013)
Authors: Shih-Hung Chen, Geert Hellings, Guido Groeseneken
Pages: 1 - 8 - ESD performance of high mobility SiGe quantum well bulk FinFET diodes and pMOS devices(2013)
Authors: Geert Hellings, Shih-Hung Chen, Guido Groeseneken
Pages: 22 - 29 - High mobility and quantum well transistors. Design and TCAD simulation(2013)
Authors: Geert Hellings, Kristin De Meyer
- Comparison of system-level ESD design methodologies – towards the efficient and ESD robust design of systems(2013)
Authors: Shih-Hung Chen, Geert Hellings, Guido Groeseneken
Pages: 213 - 222 - Improved sidewall doping with small implant angle by AsH3 Ion assisted deposition and doping process for scaled NMOS Si bulk FinFETs(2013)
Authors: Jae Woo Lee, Geert Hellings, Wilfried Vandervorst
Pages: 542 - 545 - ESD in FinFET technologies: past learning and emerging challenges(2013)
Authors: Geert Hellings, Shih-Hung Chen, Guido Groeseneken
Pages: 2
Patents
1 - 5 of 5
- Method for fabricating finfet technology with locally higher fin-to-fin pitch (Inventor)
- Breakdown-based physical unclonable function (Inventor)
- Breakdown-based physical unclonable function (Inventor)
- Scalable quantum well device and method for manufacturing the same (Inventor)
- IMPLANT FREE QUANTUM WELL TRANSISTOR, METHOD FOR MAKING SUCH AN IMPLANT FREE QUANTUM WELL TRANSISTOR AND USE OF SUCH AN IMPLANT FREE QUANTUM WELL TRANSISTOR (Inventor)