Researcher
Geert Hellings
- Disciplines:Nanotechnology, Design theories and methods
Affiliations
- Assiocated Division ESAT-INSYS (INSYS), Integrated Systems (Division)
Member
From1 Aug 2020 → 31 Dec 2011 - Electronic Circuits and Systems (ECS) (Division)
Member
From1 Aug 2020 → 30 Nov 2011 - Associated Section of ESAT - INSYS, Integrated Systems (Division)
Member
From19 Nov 2007 → 31 Dec 2011 - Department of Electrical Engineering (ESAT) (Department)
Member
From16 Apr 2005 → 18 Nov 2007
Publications
21 - 30 of 74
- ESD protection devices placed inside keep-out zone (KOZ) of through silicon via (TSV) in 3D stacked integrated circuits(2012)
Authors: Shih-Hung Chen, Geert Hellings, Guido Groeseneken
Number of pages: 8 - The implant-free quantum well field-effect transistor: Harnessing the power of heterostructures(2012)
Authors: Geert Hellings, Niamh Waldron, Geert Eneman, Andreas Schulze, Wilfried Vandervorst, Marc Heyns, Kristin De Meyer
Pages: 3326 - 3331 - Stress techniques in advanced transistor architectures: bulk FinFETs and implant-free quantum well transistors(2012)
Authors: Geert Hellings, Kristin De Meyer
Pages: 235 - 246 - Implant free SiGe-quantum well: from device concept to high-performing pFETs(2012)
Authors: Geert Hellings
Pages: 131 - 143 - Influence of InGaP and AlGaAs Schottky layers on ESD robustness in GaAs pHEMTs(2012)
Authors: Shih-Hung Chen, Geert Hellings, Guido Groeseneken
Pages: 1252 - 1254 - Reliability of SiGe Channel MOS(2012)
Authors: Jacopo Franco, Geert Hellings, Marc Heyns, Guido Groeseneken
Pages: 177 - 195 - On the Rseries extraction techniques for sub-22nm CMOS Finfet and SiGe technologies(2012)
Authors: Geert Hellings, Wilfried Vandervorst, Guido Groeseneken
Number of pages: 2 - Superior reliability and reduced time-dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications(2012)
Authors: Jacopo Franco, Geert Hellings, Marc Heyns, Guido Groeseneken
Pages: 1 - 4 - 85nm-wide 1.5mA/µm-ION IFQW SiGe-pFET: raised vs embedded Si0.75Ge0.25 S/D benchmarking and in-depth hole transport study(2012)
Authors: Geert Hellings
Pages: 163 - 164 - Junction strategies for 1x nm technology node with FINFET and high mobility channel(2012)
Authors: Naoto Horiguchi, Gerd Zschaetzsch, Yuichiro Sasaki, Ajay Kumar Kambham, Bastien Douhard, Mitsuhiro Togo, Geert Hellings, Jerome Mitard, Liesbeth Witters, Geert Eneman, et al.
Pages: 216 - 221
Patents
1 - 5 of 5
- Method for fabricating finfet technology with locally higher fin-to-fin pitch (Inventor)
- Breakdown-based physical unclonable function (Inventor)
- Breakdown-based physical unclonable function (Inventor)
- Scalable quantum well device and method for manufacturing the same (Inventor)
- IMPLANT FREE QUANTUM WELL TRANSISTOR, METHOD FOR MAKING SUCH AN IMPLANT FREE QUANTUM WELL TRANSISTOR AND USE OF SUCH AN IMPLANT FREE QUANTUM WELL TRANSISTOR (Inventor)