- Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design(2010)
Authors: Yu Yang, Chukwudi Okoro, Michal Rakowski
Pages: 140 - 144
- Impact of thinning and through silicon via proximity on high-k / metal gate first CMOS performance(2010)
Authors: Yu Yang, Guruprasad Katti, Chukwudi Okoro, Panagiotis Asimakopoulos, Ingrid De Wolf
Pages: 109 - 110
- Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances
Authors: Ingrid De Wolf, Panagiotis Asimakopoulos, Chukwudi Okoro, Yu Yang
Pages: 26 - 29
- Extraction of the appropriate material property for realistic modeling of through-Silicon-vias using ยต-Raman spectroscopy
Authors: Chukwudi Okoro, Yu Yang, Dirk Vandepitte, Bert Verlinden, Ingrid De Wolf
Pages: 16 - 18
- Process induced sub-surface damage in mechanically ground silicon wafers
Authors: Yu Yang, Bert Verlinden, Ingrid De Wolf