Title Abstract "An analog-to-digital converter circuitry, an integrated circuit device, a photoplethysmogram detector, a wearable device and a method for analog-to-digital conversion." "An analog-to-digital converter, ADC, circuitry, comprises: an integrator (102; 202) connected to a capacitor (110; 210a, 210b), the integrator (102; 202) being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator (120; 220) for comparing integrator output to the threshold; and a timer (150; 250) for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an ..." "An analog-to-digital converter circuitry, an integrated circuit device, a photoplethysmogram detector, a wearable device and a method for analog-to-digital conversion" "Qiuyang Lin, Nick Van Helleputte" "An analog-to-digital converter, ADC, circuitry, comprises: an integrator (102; 202) connected to a capacitor (110; 210a, 210b), the integrator (102; 202) being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator (120; 220) for comparing integrator output to the threshold; and a timer (150; 250) for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an ..." "A method for manufacturing of a photonic circuit and a method for performing measurements using a photonic circuit" "Silicon nitride is known to have high densities of charge traps. Filled charge traps can significantly alter the waveguide propagation loss. Our invention comprises depopulation methods that should be applied before using waveguides in any nitride based photonic application. We provide a cleaning and depopulation procedure that yields a clean waveguide surface combined with a reproducible, low-loss initial waveguide condition." "A comparator circuit" "Oscar Elisio Mattia, Davide Guermandi" "According to an aspect of the present inventive concept there is provided a comparator circuit comprising:a master latch comprising a first amplifier circuit and a first latch circuit coupled to an output of the first amplifier circuit;a slave latch comprising a second amplifier circuit having an input coupled to the output of the first amplifier circuit, and a second latch circuit coupled to an output of the second amplifier circuit; anda hysteresis compensation circuit coupled to the output of the second amplifier circuit and configured to cause a first predetermined signal level shift of ..." "An integrated circuit with 3D partitioning." "The present disclosure relates to an integrated circuit comprising: a first integrated circuit layer comprising processing cores; a second integrated circuit layer comprising memory arrays associated with processing cores, and an intermediate integrated circuit layer interconnected with the first and second integrated circuit layers and comprising memory control logic and interface circuitries for managing data exchange between the processing cores and the memory arrays." "A comparator circuit" "According to an aspect of the present inventive concept there is provided a comparator circuit comprising: a master latch comprising a first amplifier circuit and a first latch circuit coupled to an output of the first amplifier circuit; a slave latch comprising a second amplifier circuit having an input coupled to the output of the first amplifier circuit, and a second latch circuit coupled to an output of the second amplifier circuit; and a hysteresis compensation circuit coupled to the output of the second amplifier circuit and configured to cause a first predetermined signal level shift ..." "Comparator circuit" "Oscar Elisio Mattia, Davide Guermandi" "An aspect of the disclosure includes a comparator circuit comprising: a master latch comprising a first amplifier circuit and a first latch circuit coupled to an output of the first amplifier circuit; a slave latch comprising a second amplifier circuit having an input coupled to the output of the first amplifier circuit, and a second latch circuit coupled to an output of the second amplifier circuit; and a hysteresis compensation circuit coupled to the output of the second amplifier circuit and configured to cause a first predetermined signal level shift of an output signal of the first ..." "Low power logic circuit" "The invention relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a ..." "Driver circuit for driving a voltage controlled electro-optical modultor and system thereof." "The present invention relates to a driver circuit (1) for driving a voltage controlled electro-optical modulator (5), by providing an output voltage (Vout) to the electro-optical modulator (5) according to an input voltage (Vin). The driver circuit (1) comprises a supply input (SP) for receiving a DC supply voltage (VDD) with a positive supply voltage level (Vdd) and an input (IN) for receiving the input voltage (Vin), wherein the input voltage (Vin) varies between a low input level and a high input level. The driving circuit further comprises a level shifter circuit (2), which comprises two ..." "Voltage clamping circuit and use thereof" "Johan Driesen, Jordi Everts, Ratmir Gelagaev, Pieter Jacqmaer" "A voltage clamp circuit (7) is described for reflecting a voltage at an input node (N1). The voltage clamp circuit (7) comprises a circuit (9) for providing at least two currents (lmir, lref) at its output terminals (OUT1, OUT2). It further comprises at least two diodes (10, 11) each being connected to an output terminal (OUT1, OUT2) of the circuit (9) for providing at least two currents and further being connected to a line of a ground voltage (GND) and to the input node (N1) respectively. It also comprises an alternative current path connected to an output terminal (OUT2) of the circuit for ..."