Title Participants Abstract
"An anti-aliasing filter inspired by continuous-time Delta Sigma modulation" "Pavel Peev, Bart De Vuyst, Pieter Rombouts, Anas A Hamoui" "An anti-aliasing filter that incorporates a sampler is proposed to precede noise-shaping analog-to-digital converters (ADCs), such as discrete-time Δ Sigma modulators. The architecture of the proposed anti-aliasing filter is inspired by the implicit anti-aliasing filtering property of CT Δ Sigma modulators. However, contrary to CT Δ Sigma modulators, the proposed anti-aliasing filter is not sensitive to clock jitter. Furthermore, its key characteristics include: (1) higher suppression of aliases, compared to a Butterworth filter of the same order (same number of opamps); and (2) high-pass shaping of the sampling errors. Its performance advantages are derived theoretically and then confirmed through behavioural simulations."
"Continuous time delta sigma modulation with PWM pre-coding and binary g(m) blocks" "Amir Babaiefishani, Pieter Rombouts" "A very simple technique to implement the first integrator of a continuous-time delta sigma modulator (CT-DSM) is presented. In the approach, the CT-DSM is preceded by a pulse-width modulator to convert the input signal to a pseudo-digital continuous time waveform. As a result, the first integrator of the DSM can be implemented with a capacitor and a switched current source, with inherent linearity. To illustrate the concept, it has been applied to the design of a second-order CT-DSM in 65 nm CMOS technology."
"Multirate Cascaded Discrete-Time Lowpass Delta Sigma Modulator for GSM/Bluetooth/UMTS" "Lynn Bos, Pieter Rombouts, Arnd Geis, Alonso Morgado, Julien Ryckaert" "This paper shows that multirate processing in a cascaded discrete-time 16 modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time 16 modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded 16 modulator enables the power efficient implementation of multiple communication standards. The advantages of multirate cascaded 16 modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time 16 modulator. A 2-1 multirate low-pass cascade, with a sa"
"A 5-MHz 11-Bit Self-Oscillating sigma delta modulator with a delay-based phase shifter in 0.025 mm(2)" "Bart De Vuyst, Pieter Rombouts" "Self-oscillating Sigma Delta modulators are a class of Sigma Delta modulators that combines noise shaping with pulsewidth modulation (PWM). Moreover, in such a modulator, the PWM carrier is generated by a self-oscillation mode that is deliberately introduced. In our approach, this self-oscillation is accurately controlled by a digital delay in the feedback loop. The concept is elaborated for a second-order self-oscillating Sigma Delta modulator with 5-MHz bandwidth. Here, the clock frequency equals 850 MHz, but the loop only has to process signals that are maximally at the self-oscillation frequency (at 106.25 MHz). An additional key element in this design is the use of a feedback FIRDAC which reduces the jitter sensitivity and further relaxes the slewing requirements of the first opamp in the loop. The prototype modulator is fabricated in a 0.18-mu m CMOS process and achieves a dynamic range of 66 dB. Due to the simplicity of the circuit, the modulator core area is only 0.025 mm(2). The power consumption of the modulator is 6 mW."
"Design and implementation of a band-pass sigma delta modulator with distributed resonators" "Enrique Prefasi, Luis Hernandez, Stijn Reekmans, Pieter Rombouts" "Continuous time band-pass sigma delta converters require the realization of high frequency resonators, which have been usually implemented with g (m)-C or LC circuits. However, transmission lines have been for a long time a standard way to implement high Q resonators in RF circuits. Recently, some continuous-time sigma-delta (SD) modulator architectures using transmission lines have been proposed. Theoretical analyses have shown that this kind of architectures share some of the properties of both continuous-time (CT) and discrete-time (DT) modulators. On the other hand they have specific implementation problems which are not present in other modulator architectures. This paper makes a brief review of the particularities of these modulators and shows the experimental results of a band-pass modulator implemented in BiCMOS technology. As an advantage compared to standard continuous time designs, this modulator can be operated as a subsampling ADC, displays a better immunity to clock jitter and is tolerant to loop delay"
"A double-sampling cross noise-coupled sigma delta modulator with a reduced amount of opamps" "Maarten De Bock, Pieter Rombouts" "his paper presents the design of a second order double-sampling split path Sigma Delta modulator with cross noise-coupling. The power budget for the double-sampling is reduced by using bilinear integrators, while cross noise-coupling between the two modulator loops increases the noise shaping to third order. The implementation of the noise-coupling is incorporated into the second integrator using a novel delaying feed-forward circuit. The complete modulator is integrated in a 130nm CMOS technology and operates at a 120 MHz clock frequency. It achieves 77.8dB dynamic range and 71.4dB SNDR over a 5MHz bandwidth."
"A selectable-bandwidth 3.5 mW, 0.03 mm2 self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth" "Georges Gielen" "In this paper we present a dual-mode third-order continuous time ε Upsigma δ modulator that combines noise-shaping and pulse-width-modulation (PWM). In our 0.18 μm CMOS prototype chip the clock frequency equals 1 GHz, but the PWM carrier is only around 125 MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10 MHz. In the 5 MHz mode the peak SNDR equals 64 dB and the dynamic range 71 dB. In the 10 MHz mode the peak SNDR equals 58 dB and the DR 65 dB. This performance is achieved at an attractively low silicon area of 0.03 mm 2 and a power consumption of 3.5 mW. © 2012 Springer Science+Business Media, LLC."
"A 250 mV 7.5 mu W 61 dB SNDR SC Delta Sigma Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS" "Fridolin Michel, Michiel Steyaert" "An ultra-low voltage switched-capacitor (SC) Delta Sigma converter running at a record low supply voltage of only 250 mV is introduced. System level aspects are discussed and special circuit techniques described, that enable robust operation at such a low supply voltage. Using a SC biasing approach, inverter-based integrators are realized with overdrives close to the transistor threshold voltage V-th while compensating for process, voltage and temperature (PVT) variation. Biasing voltages are generated on-chip using a novel level shifting circuit, that overcomes headroom limitations due to saturation voltage V-sat. With an oversampling ratio (OSR) of 70 and a sampling frequency (fs) of 1.4 MHz at 250 mV power supply the converter achieves 61 dB SNDR in 10 kHz bandwidth while consuming a total power of 7.5 mu W."
"Multirate cascaded discrete-timelowpass delta sigma modulator for GSM/ bluetooth/ UMTS" "Yves Rolain" "This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards. The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2V90 nmCMOStechnology with a core area of 0.076mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ. © 2006 IEEE."
"Genetic algorithm for electro-mechanical co-optimization of a MEMS accelerometer comprising a mechanical motion pre-amplifier with a 2nd-order sigma delta modulator" "Chen Wang, Michael Kraft"