Title Affiliations Abstract "High-frequency IC packaging equipment for mm-wave applications." "Electronic Circuits and Systems (ECS)" "High-frequency IC packaging equipment based on flip-chip technology will support and strengthen the research on integrated CMOS solutions for mm-wave applications in the 30- 300GHz frequency range." "Exploratie naar de integreerbaarheid van Physically Unclonable Functions op chip." "Ingrid Verbauwhede" "ESAT - COSIC, Computer Security and Industrial Cryptography" "No two physical objects are exactly the same, even when manufactured with a nominally identical process. For example, two sheets of paper that are indistinguishable with the naked eye, still differ considerably in their nanoscale fiber structures. Although manufacturing variability is usually undesired, the associated ability to uniquely identify a physical object, which is constrained to an integrated circuit (IC) in this thesis, can be leveraged for security purposes. To facilitate the registration of unique features, a so-called physically unclonable function (PUF) can be implemented on the IC. A PUF circuit is designed to be sensitive to process variations, i.e., challenged with a binary input, it provides a binary, device-unique response. This building block can hence be understood as the silicon equivalent of human biometrics.PUFs can augment the security architecture of an ever-increasing number of electronic devices that access our personal data and/or represent our identities. This includes but is not limited to smartphones, credit cards, access badges, the sensors and actuators of automated home, and medical implants. PUFs usually need to team up with other building blocks, e.g., true random number generators (TRNGs), cryptographic algorithms, error-correcting codes, non-volatile memory (NVM), etc. We analyze the security of such multi-component systems in a format that allows for comparisons among proposals that have similar or identical objectives. Numerous newly revealed flaws and attacks are presented throughout this thesis. On the bright side, the lessons learned can help improve the quality of future PUF-based systems." "Multi-GHz Bandwidth Power-Efficient Nyquist A/D Conversion: Architecture and Circuit Innovations in Deep-Scaled CMOS" "Filip Tavernier, Michiel Steyaert" "Electronic Circuits and Systems (ECS)" "The Analog-to-Digital Converter (ADC) is considered the cornerstone of modern electronics due to its fundamental role in virtually any application requiring the transfer of information between the physical (analog) world and the processing (digital) world. This task comes with myriad challenges due to the complex multi-functional ADC nature, further exacerbated when the relevant applications demand stringent performance requirements. Furthermore, bridging the analog and digital worlds fundamentally implies that ADCs must deal with the non-idealities of the former while keeping up with the advancements of the latter. The rapidly accelerating trend for broader-band signals and software-defined systems has spurred the need for ADCs operating in the multi-GHz sample rate and bandwidth regime. Such converters are highly demanded by applications in the realm of next generation high-speed wireless and wireline communications, automotive radar as well as high-end instrumentation, and have attracted a growing attention from both industries and research institutes. The ever-increasing desire of these systems is to maximize speed, while progressively improving the accuracy and the power efficiency, pushing the performance dimensions to new benchmarks. Meeting these performance requirements at the multi-GHz regime comes with numerous challenges at the circuit, architecture and system levels. On top, the constant technology down-scaling, dictated by the demand for higher functionality at a reduced power and cost, and the improvement in digital performance, exacerbates these challenges for traditional analog-intensive solutions.This dissertation follows an analytical approach to propose innovative circuit, architecture and system solutions in deep-scaled CMOS and maximize the accuracy·speed÷power of multi-GHz sample rate and bandwidth ADCs. The approach starts by identifying the major error sources of any practical converter's circuits and quantitatively analyzing their significance on the overall performance. This establishes the fundamental accuracy-speed-power limits imposed by circuits and builds an understanding as to what may be achievable from the elementary building blocks in a converter. The analysis is extended to the architectural level by introducing models to estimate and compare the accuracy-speed-power limits of high performance architectures, such as flash, SAR, pipeline and pipelined-SAR. From these models, the SAR comes out as the optimum architecture for a low-to-medium resolution across a wide range of sample rates, while for a medium-to-high resolution, the >2-stage pipelined-SAR hybrid emerges as a promising candidate. To gain insight on the system level and peripheral blocks, a model is introduced to quantitatively compare interleaver architectures, namely direct, de-multiplexing and re-sampling, in terms of achievable bandwidth and sampling accuracy. The strength of the newly introduced models is greatly enhanced by adding technology effects from four deep-scaled CMOS processes; 65nm, 40nm, 28nm and 16nm, building further insight in both the architecture as well as the process choice for optimum performance at given specifications. To demonstrate the feasibility of the proposed solutions, three multi-GHz prototype ICs are implemented in 28nm CMOS and verified with measurements, while one more is realized in 16nm FinFET CMOS. (1) A 28nm CMOS three-stage triple-latch comparator with a high total gain, a reduced device stacking and parallel direct/feed-forward paths is introduced, which improves altogether the absolute delay, delay slope, and robustness over conventional topologies, while allowing for a similar noise and competitive power compared to the state-of-the-art. (2) A 7-bit single-channel SAR ADC is proposed with a semi-asynchronous processing, a dual-loop bootstrapped input switch, a triple-tail dynamic comparator and a Unit-Switch-Plus-Cap DAC. These features enable a 1.25GS/s sample rate and a >5GHz bandwidth, allowing for a smooth integration into a larger system. The 28nm CMOS prototype ADC compares favorably to the state-of-the-art by achieving among the highest sample rates and the lowest accuracy degradation across the entire band of interest, with an on par overall power dissipation, area and FoM. (3) A 5GS/s 12-bit passive-sampling RF ADC tackles the challenges of wide input bandwidth and high spectral purity in absence of a front-end buffer with a minimized resistance/capacitance network. An on-chip clock conditioning/distribution chain with low jitter ensures sampling purity, while a 3-stage pipelined-SAR hybrid sub-ADC enhances power efficiency. A combined custom analog/synthesized digital calibration improves the spectral performance over the entire band of interest. The 28nm CMOS prototype demonstrates a >6GHz input bandwidth and significantly advances the state-of-the-art among wideband TI RF ADCs. (4) A 16nm FinFET CMOS analog/RF front-end achieves a >30GHz bandwidth, while maintaining an |IMD3|>61dB and a NSD" "Automatic Defect-Oriented Test Generation for Analog and Mixed-Signal Integrated Circuits" "Georges Gielen" "ESAT - MICAS, Microelectronics and Sensors, Electronic Circuits and Systems (ECS)" "The fabrication process of modern integrated circuits (ICs) is not perfect and the resulting manufacturing yield never reaches 100%. Therefore, manufactured ICs have to be tested in order to filter out the defective chips before they reach the electronic market. Therefore, solutions are needed to simultaneously improve the test coverages and reduce the time required to design these tests.In this research, we develop a framework based on the defect-oriented methodology. By modeling the physical defects which can occur in an IC, the effects a defective circuit can be simulated. Based on this simulated behaviors, structural tests can be generated i.e. tests targeting the defects of the circuit instead of the functionality of the circuit.On the one hand, an automatic test signal generation method is developed by partitioning the considered circuits into sub-circuits. Then, the Kirchhoff's current law describing the interactions of these sub-circuits are solved with interval analysis. On the other hand, a set of building blocks enhancing the observability and controllability of the circuits are studied in order to automate the injection of test hardware into the circuit. As a result, the combination of the test signal generation and test hardware generation forms a framework enabling the automatic test generation for the targeted IC." "GARLIC: a Generic ARchitecture of a Low-loss Integrated Converter, eliminating Vampire Power" "Michiel Steyaert" "Electronic Circuits and Systems (ECS)" "Electronic devices and appliances are wasting a lot of energy while they are in standby mode. This so-called vampire energy can be higher than the energy that the device consumes in its operational mode due to the long standby time and the short active mode for typical applications. The reason for this unwanted high power consumption lies in the electronic circuit that converts the high AC mains voltage into a low DC voltage that can supply power to the electronic device. While optimized to work in the active mode, the efficiency of this voltage converter drops below 10 % or even below 1 % in the standby mode. The same holds when the input voltage is a high DC voltage, such as in the case of an electric car battery that directly supplies power the various car electronic systems.Manufacturers of voltage converters are struggling to reduce the energy losses in standby mode. Regulations imposed by the European Commission and the US Department of Energy are becoming more and more stringent, with the goal to reduce energy waste, CO2 emission and electricity cost. Complying with these standby power regulations is seen as a major challenge for the power converter industry. The obvious solution of adding a parallel converter that kicks in only in the standby mode, for which it would be optimized, has proven impossible without an inacceptable inflation of volume and cost.This is where MICAS steps in. We propose a solution that is based on a CMOS chip, which is intrinsically small, cheap and low power. Based on previous research performed in MICAS, we will develop a Generic ARchitecture for a Low-loss Integrated Converter, or GARLIC, eliminating the vampire energy in electronic devices and appliances by taking care of the power supply in the standby mode. At the end of the project, we will demonstrate a highly efficient prototype system that meets the current and future challenges of the AC/DC and DC/DC converter markets.The scientific challenges that need to be tackled during the project are mainly the compatibility of the CMOS chip with the high input voltage and the capacity to deliver enough output power for a large variety of applications. We have already proven the basic concepts that help answer these challenges, but in GARLIC, we will evolve towards the full system level and towards the validation in a demo setting.The valorization approach will follow the proven MICAS strategy. The research results, backed by the hardware demonstration, will be transferred to the industry through licensing, via close collaborations with both large component providers as well as smaller, but highly innovative chip companies. For the first group, targeted companies are e.g. ON Semiconductor and Infineon, who can weigh on the supply chains in the electronics industry in order to realise innovations like the one we propose. The second group contains companies such as Ansem, ICsense and MinDCet. All these companies have already shown interest in the commercialisation of GARLIC." "Thermal Management of Integrated CMOS-Si Photonics Optical Transceivers" "Ingrid De Wolf" "Structural Composites and Alloys, Integrity and Nondestructive Testing (SCALINT)" "The infrastructure behind the internet are data centres, where data are stored and processed centrally. Transporting large amounts of data inside the data centre requires a significant amount of energy. To improve the energy efficiency of data transport, the classical electrical connections are being replaced with optical fibres. Traditional electrical input-output (I/O) faces multiple bottlenecks: the bandwidth-distance-power trade-off and chip pin count. Silicon photonics, the technology to manufacture integrated photonic circuits using CMOS process technology, promises to alleviate these bottlenecks and provide low propagation loss, high bandwidth optical I/O links. Recent advances in packaging technologies allow the tight integration of Si photonics transceiver chips with the host IC in a single chip package. These co-packaged optics enable the high bandwidth required for future data centres as well as the reduction of the package footprint. The Si photonic elements are however significantly affected by changes in local and ambient temperature, e.g. caused by the highly non-uniform power generation in the ASIC or FPGA CMOS chip, the laser sources, and the optical devices themselves. Temperature changes can cause a wavelength shift which leads to an optical power loss due to wavelength mismatch and to laser power degradation, which introduces more challenges for the thermal management of these co-packaged optics. In the first part, we study the thermal behaviour of photonic devices used in optical transceivers. Ring-based devices (i.e. ring- modulators and filters) rely on accurate spectral alignment with the laser source. To achieve wavelength locking, the waveguide temperature is controlled with integrated heaters. Through thermo-optical modelling, strategies for improving the heater efficiency are proposed, as well as methods for improving the electromigration lifetime of the heaters. We also study the thermo-optical stability of electro-absorption modulators and ring modulators at high optical power, and propose methods for minimising self-heating. Finally, interferometric devices, such as the Mach- Zehnder interferometer, are also subjected to heater optimisation.In the second part, the thermal aspects of two different laser sources for optical transceivers are investigated. First, a nano-scale thermal model is developed and validated for the nano-ridge laser, a novel III-V on Si monolithic laser. With the model, device reliability weak spots are identified, and design changes are proposed for self-heating mitigation. Secondly, thermal characterisation of hybrid InP-Si lasers is carried out and benchmarked against different state-ofthe- art integration approaches. The analysis is done both for single-channel and multi-channel laser dies, and the optimal thermal design of a multi-channel light source is investigated. In the third and final part, we zoom out and combine multiple photonic devices in integrated photonic circuits. Because there is no off-the-shelf solution for multiscale thermo-optical simulation, new simulation tools are developed. Firstly, thermal-equivalent RC-networks are built for fast circuit-level simulation, considering device-level dynamics and thermal crosstalk. Secondly, multiple machine learning algorithms are trained with finite element simulation data to build extremely compact and black-box models, resulting in three orders of magnitude computational time decrease. The developed models are applied to analyse two optical transceiver designs, for which the impact of 3D electronicphotonic integration is quantified, as well as the impact of thermal crosstalk. In the last chapter all results are combined into a thermo-optical link model, that allows for the calculation of the link efficiency improvement based on the results in this thesis. Current state-of-the-art optical transceivers require 3 pJ/bit, while a thermally optimised design can achieve sub-1 pJ/bit, improving the efficiency more than threefold." "Design of EMI resilient automotive integrated circuits in SOI technology" "Wim Dehaene" "Electronic Circuits and Systems (ECS)" "Electromagnetic compatibility (EMC) problems are the third origin of redesigning integrated circuits, as they are the source of interference problems, noise emission, and sensitivity. Due to the technology trends, EMC problems also become more complicated because there are fundamental constraints due to high-speed clocks, the high number of electronic systems, chip complexity, lower supply voltage, and safety users. In this case, EMC has become a major concern for designing ICs which requires strong skills in electromagnetism, electricity, and microelectronics. This is a very vast subject and different researches have been performed in this area. Hence, several guidelines and standards have been developed including some techniques such as shielding and filtering. However, the problem is that they are concentrated on a rule-based approach and even though these rules are right, there is no guarantee that they are sufficient. So we cannot be sure that a new system will be reliable and safe or not. The goal of my Ph.D. is to find a risk-based approach for electromagnetic emission and immunity issues for designing ICs. From another point of view, up to now, the electronic devices have been evaluated just when they are new but the environmental factors including aging, vibration, and temperature or changes due to maintenance, repairs, and upgrades are not considered adequately. Moreover, different simultaneous EMC problems cannot be assessed with standards. In this thesis, I intend to rectify these shortcomings by considering the whole system over its lifecycle. To this end, I should also pass some courses to reach a correct view of the real problem which is an interdisciplinary subject. Analog and Mixed-Signal Electronics for Signal Processing, Electromagnetic Interference in Analogue and Digital Systems, and Design of Digital Integrated Circuits are scientific courses that I am supposed to follow." "High voltage mixed signal integrated circuits in a hybrid technology" "Kris Myny" "Micro- and Nano Systems (MNS)" "The main ambition of this PhD project is to elaborate several design concepts towards high voltage ICs, taking advantage of the novel developed hybrid technology in the ERC project ORISON. The novel technology combines monolithically Si CMOS and Indium-Gallium-Zinc-Oxide (IGZO) transistors. Virtual design libraries will be envisioned for system-technology co-optimization research activities, evaluating those concepts for different application fields. The novel libraries will be demonstrated in high-voltage interfaces for wearable healthcare applications, robotics, and sensor technology." "ORGANIC: Opportunities for Research towards GAllium-Nitride Integrated Circuits" "Patrick Reynaert" "Electronic Circuits and Systems (ECS)" "GaN is being considered as a promising technology in power switching and RF power applications. GaN devices can operate at higher temperatures, higher power densities, higher voltages and higher frequencies than their silicon based couterparts. Already today some products based on GaN devices are on the market. There remains however a tremendous opportunity in this field, namely a higher degree of monolithic integration. Current GaN devices are mostly single components or MMIC's with very limited complexity. These components have to be combined with driver and control circuitry fabricated in another technology. This leads to a significant loss in performance (especially speed and efficiency) and to an increase in complexity and cost. As the evolution of silicon technologies has shown, a high degree of integration results in lower cost, higher speed and lower power electronic systems. In this field, MICAS can build upon a wealth of expertise in the design of analog and mixed-signal integrated circuits. In this C3 project, MICAS will leverage its design know-how to the GaN field, leading to a unique and crucial position in the GaN ecosystem. We will explore technology options, develop design concepts and architectures for large-scale high-complexity GaN integrated circuits, and validate the research through the design and realization of two integrated GaN-IC demonstrators. The valorization of the research results of ORGANIC will be mainly realized through bilateral industrial projects with companies that are active in the field of GaN components." "Spray coating as an enabler for heterogeneous semiconductor systems-on-chip & bioelectronics" "Günther Roelkens" "Department of Information technology" "The goal of this project is to develop the spray coating of photoresist, ultra-thin DVS-BCB adhesive bonding layers and other advanced polymers on 200 mm Si wafers or small samples comprising photonic or electronic integrated circuits (ICs), or MEMS. This will enable the realization of heterogeneous semiconductor systems-on-chip for application in optical transceivers, smart sensors and advanced electronic integrated circuits (analogue frontends), by means of micro-transfer printing technology. The main applications are the integration of III-V semiconductor photonic (electronic) components on silicon photonic (electronic) ICs, but the integration of other material systems of great importance for photonics (electro-optic materials, magneto-optic materials) will be envisioned as well, all enabled by spray coating and micro-transfer printing. The spray coating is a key technology to enable such heterogeneous systems-on-chip as it is the only technique that allows a uniform conformal coating of thin polymer layers on high-topography wafer surfaces, which is essential for micro-transfer printing. Next to this the use of the tool for bio-electronic applications (specifically neural interfaces) will be evaluated, a market with a large growth potential. Specifically the spray coating of semiconducting and conducting polymers on conformable substrates will be developed."