Circuit-Technology Co-optimization of SRAM Design in Advanced CMOS Nodes KU Leuven
The impressive growth of the semiconductor industry in the past few decades has been driven by CMOS technology scaling. Miniaturizing the CMOS devices provides larger integration density, higher performance while lower the power consumption. However, as CMOS scales down to node N5 and beyond, gate length scaling becomes increasingly difficult if not impossible. Furthermore, the resistance of local interconnect in advanced nodes becomes the ...