POWER-AWARE EVALUATION FLOW FOR DIGITAL DECIMATION FILTER ARCHITECTURES FOR HIGH-SPEED ADCS KU Leuven
The raising cost of the latest technology nodes as well as the design cost associated has motivated an increasing push for flexible radio implementations. In this context, Sigma-Delta (ΣΔ) ADCs have emerged as a promising alternative to direct conversion. In this work a novel wireless receiver architecture based on an RF bandpass ΣΔ is considered. One of the key blocks of this architecture is the digital decimation filter which needs to run at ...