Publications
Chosen filters:
Chosen filters:
Characterization and commissioning of the SST1M camera for the Cherenkov Telescope Array Vrije Universiteit Brussel
The Cherenkov Telescope Array (CTA), the next generation very high energy gamma-rays observatory, will consist of three types of telescopes: large (LST), medium (MST) and small (SST) size telescopes. The SSTs are dedicated to the observation of gamma-rays with energy between a few TeV and a few hundreds of TeV. The SST array is expected to have 70 telescopes of different designs.
The single-mirror small size telescope (SST-1 ...
Multi-GHz Bandwidth Power-Efficient Nyquist A/D Conversion: Architecture and Circuit Innovations in Deep-Scaled CMOS KU Leuven
The Analog-to-Digital Converter (ADC) is considered the cornerstone of modern electronics due to its fundamental role in virtually any application requiring the transfer of information between the physical (analog) world and the processing (digital) world. This task comes with myriad challenges due to the complex multi-functional ADC nature, further exacerbated when the relevant applications demand stringent performance requirements. ...
A Simplified Approach to Concurrent Dual-Band Power Amplifiers Digital Predistortion Vrije Universiteit Brussel
The increasing demand for wider bandwidth in the current wireless networks and the need to work simultaneously with different networks impose many design challenges for power amplifiers (PA) design and the digital predistortion (DPD) in many aspects. The analog-to-digital converter (ADC) sampling speed for conventional DPD has to be several times the original signal bandwidth in order to cover the out-of-band intermodulation components caused by ...
A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion KU Leuven
An analog-to-digital conversion (ADC) scheme based on asynchronous Delta Sigma modulation and time-to-digital conversion is presented. An asynchronous Delta Sigma modulator translates the analog input to an asynchronous duty-cycle modulated signal. Next, the edge locations are digitally measured using a time-to-digital converter (TDC). This information is then digitally processed into a conventional digital signal. The performance of this novel ...
A 5GS/s 7.2 ENOB Time-Interleaved VCO-based ADC Achieving 30.5fJ/cs KU Leuven
This article presents an eight-channel time-interleaved voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC), achieving 7.2 effective number of bits (ENOBs) at 5 GS/s in 28-nm CMOS. A high-speed ring oscillator with feedforward cross-coupling and a shared tail transistor is combined with an asynchronous counter in order to improve the resolution while minimizing the power consumption. Asynchronous double sampling is used ...
A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv-step KU Leuven
© 2019 IEEE. Technology scaling has been very beneficial for digital circuits both in terms of speed and power. Traditional analog techniques however are challenged by the ever-decreasing supply voltages. Highly digital VCO-based ADCs are able to benefit directly from improved digital performance [1]; however, the resolution and sampling rate of state-of-the-art VCO-based designs are insufficient for most applications. This paper presents a ...
An 11GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28nm CMOS KU Leuven
This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, ...
A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS Vrije Universiteit Brussel
High-speed low-resolution ADCs are an essential part of receivers for wireless standards such as UWB. These converters have to combine the stringent speed specifications with the demand for low power consumption. Flash architectures are often chosen because they offer the largest speed. However, in this architecture, area and power depend exponentially on the resolution since the comparators are often the largest contributor to the overall power ...