Transient-induced Latchup (TLU) Exploration in System-Technology Co-Optimization (STCO) Scaling Era KU Leuven
Due to the device geometry scaling and newly introduced process options, latchup (LU) safe designs have become an increasingly challenging task of high-voltage (HV) or I/O circuit blocks in advanced bulk CMOS technologies. The bulk CMOS technologies have evolved over several process generations to provide cheaper products, smaller area, lower standby leakage, but more operating performance of computation speed and power [1]. The dimension of ...