A 12 Bit 4.7-MS/s 260.5μW Digital Feed-Forward Incremental-ΣΔ-SAR ADC in 0.13μm CMOS for Image Sensors Vrije Universiteit Brussel
This paper presents a 12 bit, 4.7 MS/s Digital Feed-Forward Incremental ΣΔ - Successive Approximation Register (DFF I- ΣΔ -SAR) Analog-to-Digital Converter (ADC) for column readout of image sensors. An input range detection phase and a new switching scheme for the DAC in the first stage allow reaching the desired 4 bit resolution of the I- ΣΔ stage with an Over Sampling Ratio (OSR) of 8. A second stage SAR converts the I- ΣΔ residue voltage ...